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Fix comment. Other formatting changes. No functionality changes.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57785 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bill Wendling
2008-10-19 20:34:04 +00:00
parent 0e3da1def4
commit 181b627f62
1 changed files with 6 additions and 5 deletions
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11
lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
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@ -2207,7 +2207,7 @@ void SelectionDAGLowering::visitUIToFP(User &I) {
} }
void SelectionDAGLowering::visitSIToFP(User &I){ void SelectionDAGLowering::visitSIToFP(User &I){
// UIToFP is never a no-op cast, no need to check // SIToFP is never a no-op cast, no need to check
SDValue N = getValue(I.getOperand(0)); SDValue N = getValue(I.getOperand(0));
MVT DestVT = TLI.getValueType(I.getType()); MVT DestVT = TLI.getValueType(I.getType());
setValue(&I, DAG.getNode(ISD::SINT_TO_FP, DestVT, N)); setValue(&I, DAG.getNode(ISD::SINT_TO_FP, DestVT, N));
@ -3079,6 +3079,7 @@ SelectionDAGLowering::visitLog2(CallInst &I) {
void void
SelectionDAGLowering::visitLog10(CallInst &I) { SelectionDAGLowering::visitLog10(CallInst &I) {
SDValue result; SDValue result;
if (getValue(I.getOperand(1)).getValueType() == MVT::f32 && if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
SDValue Op = getValue(I.getOperand(1)); SDValue Op = getValue(I.getOperand(1));
@ -4221,13 +4222,13 @@ SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
else if (NumZeroBits >= RegSize-9) else if (NumZeroBits >= RegSize-9)
isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8
else if (NumSignBits > RegSize-16) else if (NumSignBits > RegSize-16)
isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
else if (NumZeroBits >= RegSize-17) else if (NumZeroBits >= RegSize-17)
isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
else if (NumSignBits > RegSize-32) else if (NumSignBits > RegSize-32)
isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
else if (NumZeroBits >= RegSize-33) else if (NumZeroBits >= RegSize-33)
isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
if (FromVT != MVT::Other) { if (FromVT != MVT::Other) {
P = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, P = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext,