6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-07-24 06:25:18 +00:00
Code Issues Projects Releases Wiki Activity

pr9367: Add missing predicated BLX instructions.

Browse Source 
Patch by Jyun-Yan You, with some minor adjustments and a testcase from me.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126915 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bob Wilson
2011-03-03 01:41:01 +00:00
parent cb1c195f53
commit 181d3fe727
4 changed files with 27 additions and 4 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
View File

@@ -809,8 +809,10 @@ static bool DisassembleBrMiscFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
if (Opcode == ARM::BX_RET || Opcode == ARM::MOVPCLR)
return true;
// BLXr9 and BX take one GPR reg.
if (Opcode == ARM::BLXr9 || Opcode == ARM::BX) {
// BLX and BX take one GPR reg.
if (Opcode == ARM::BLXr9 || Opcode == ARM::BLXr9_pred ||
Opcode == ARM::BLX || Opcode == ARM::BLX_pred ||
Opcode == ARM::BX) {
assert(NumOps >= 1 && OpInfo[OpIdx].RegClass == ARM::GPRRegClassID &&
"Reg operand expected");
MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,