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convert PPC::BCC to use the 'pred' operand instead of separate predicate

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value and CR reg #.  This requires swapping the order of these everywhere
that touches BCC and requires us to write custom matching logic for
PPCcondbranch :(


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31835 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2006-11-17 22:37:34 +00:00
parent 289c2d5f45
commit 18258c6404
5 changed files with 25 additions and 14 deletions
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4
lib/Target/PowerPC/PPCBranchSelector.cpp
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@ -126,8 +126,8 @@ bool PPCBSel::runOnMachineFunction(MachineFunction &Fn) {
// 1. PPC branch opcode
// 2. Target MBB
MachineBasicBlock *DestMBB = MBBI->getOperand(2).getMachineBasicBlock();
PPC::Predicate Pred = (PPC::Predicate)MBBI->getOperand(1).getImm();
unsigned CRReg = MBBI->getOperand(0).getReg();
PPC::Predicate Pred = (PPC::Predicate)MBBI->getOperand(0).getImm();
unsigned CRReg = MBBI->getOperand(1).getReg();
int Displacement = OffsetMap[DestMBB->getNumber()] - ByteCount;
bool ShortBranchOk = Displacement >= -32768 && Displacement <= 32767;

12
lib/Target/PowerPC/PPCISelDAGToDAG.cpp
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@ -1001,11 +1001,21 @@ SDNode *PPCDAGToDAGISel::Select(SDOperand Op) {
getI32Imm(BROpc) };
return CurDAG->SelectNodeTo(N, SelectCCOp, N->getValueType(0), Ops, 4);
}
case PPCISD::COND_BRANCH: {
AddToISelQueue(N->getOperand(0)); // Op #0 is the Chain.
// Op #1 is the PPC::PRED_* number.
// Op #2 is the CR#
// Op #3 is the Dest MBB
AddToISelQueue(N->getOperand(4)); // Op #4 is the Flag.
SDOperand Ops[] = { N->getOperand(1), N->getOperand(2), N->getOperand(3),
N->getOperand(0), N->getOperand(4) };
return CurDAG->SelectNodeTo(N, PPC::BCC, MVT::Other, Ops, 5);
}
case ISD::BR_CC: {
AddToISelQueue(N->getOperand(0));
ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
SDOperand CondCode = SelectCC(N->getOperand(2), N->getOperand(3), CC);
SDOperand Ops[] = { CondCode, getI32Imm(getPredicateForSetCC(CC)),
SDOperand Ops[] = { getI32Imm(getPredicateForSetCC(CC)), CondCode,
N->getOperand(4), N->getOperand(0) };
return CurDAG->SelectNodeTo(N, PPC::BCC, MVT::Other, Ops, 4);
}

4
lib/Target/PowerPC/PPCISelLowering.cpp
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@ -2614,7 +2614,7 @@ PPCTargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
unsigned SelectPred = MI->getOperand(4).getImm();
BuildMI(BB, PPC::BCC, 3)
.addReg(MI->getOperand(1).getReg()).addImm(SelectPred).addMBB(sinkMBB);
.addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
MachineFunction *F = BB->getParent();
F->getBasicBlockList().insert(It, copy0MBB);
F->getBasicBlockList().insert(It, sinkMBB);
@ -2890,8 +2890,8 @@ SDOperand PPCTargetLowering::PerformDAGCombine(SDNode *N,
}
return DAG.getNode(PPCISD::COND_BRANCH, MVT::Other, N->getOperand(0),
DAG.getRegister(PPC::CR6, MVT::i32),
DAG.getConstant(CompOpc, MVT::i32),
DAG.getRegister(PPC::CR6, MVT::i32),
N->getOperand(4), CompNode.getValue(1));
}
break;

6
lib/Target/PowerPC/PPCInstrInfo.cpp
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@ -260,13 +260,13 @@ void PPCInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
BuildMI(&MBB, PPC::B, 1).addMBB(TBB);
else // Conditional branch
BuildMI(&MBB, PPC::BCC, 3)
.addReg(Cond[0].getReg()).addImm(Cond[1].getImm()).addMBB(TBB);
.addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
return;
}
// Two-way Conditional Branch.
BuildMI(&MBB, PPC::BCC, 3)
.addReg(Cond[0].getReg()).addImm(Cond[1].getImm()).addMBB(TBB);
.addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
BuildMI(&MBB, PPC::B, 1).addMBB(FBB);
}
@ -285,6 +285,6 @@ bool PPCInstrInfo::
ReverseBranchCondition(std::vector<MachineOperand> &Cond) const {
assert(Cond.size() == 2 && "Invalid PPC branch opcode!");
// Leave the CR# the same, but invert the condition.
Cond[1].setImm(PPC::InvertPredicate((PPC::Predicate)Cond[1].getImm()));
Cond[0].setImm(PPC::InvertPredicate((PPC::Predicate)Cond[0].getImm()));
return false;
}

13
lib/Target/PowerPC/PPCInstrInfo.td
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@ -34,7 +34,7 @@ def SDT_PPCvcmp : SDTypeProfile<1, 3, [
]>;
def SDT_PPCcondbr : SDTypeProfile<0, 3, [
SDTCisVT<1, i32>, SDTCisVT<2, OtherVT>
SDTCisVT<0, i32>, SDTCisVT<2, OtherVT>
]>;
def SDT_PPClbrx : SDTypeProfile<1, 3, [
@ -358,11 +358,12 @@ let isBranch = 1, isTerminator = 1, hasCtrlDep = 1,
[(br bb:$dst)]>;
}
// BCC is formed before branch selection, it is turned into Bxx below.
// 'opc' is a 'PPC::Predicate' value.
def BCC : Pseudo<(ops CRRC:$crS, u16imm:$opc, target:$dst),
"${:comment} BCC $crS, $opc, $dst",
[(PPCcondbranch CRRC:$crS, imm:$opc, bb:$dst)]>;
// BCC represents an arbitrary conditional branch on a predicate.
// FIXME: should be able to write a pattern for PPCcondbranch, but can't use
// a two-value operand where a dag node expects two operands. :(
def BCC : Pseudo<(ops pred:$cond, target:$dst),
"b${cond:cc} ${cond:reg}, $dst",
[/*(PPCcondbranch CRRC:$crS, imm:$opc, bb:$dst)*/]>;
def BLT : BForm<16, 0, 0, 12, 0, (ops CRRC:$crS, target:$block),
"blt $crS, $block", BrB>;