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[PowerPC] Add asm support for cache-inhibited ld/st instructions

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Add assembler support for the fixed-point cache-inhibited load/store
instructions. These are hypervisor-level only, so don't get too excited ;)

Fixes PR21650.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222976 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Hal Finkel 2014-11-30 10:15:56 +00:00
parent 73642a847d
commit 186abcb853
3 changed files with 62 additions and 0 deletions
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18
lib/Target/PowerPC/PPCInstrInfo.td
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@ -3234,6 +3234,24 @@ def MTDCR : XFXForm_1<31, 451, (outs), (ins gprc:$RT, i32imm:$SPR),
def ATTN : XForm_attn<0, 256, (outs), (ins), "attn", IIC_BrB>;
def LBZCIX : XForm_base_r3xo<31, 853, (outs gprc:$RST), (ins gprc:$A, gprc:$B),
"lbzcix $RST, $A, $B", IIC_LdStLoad, []>;
def LHZCIX : XForm_base_r3xo<31, 821, (outs gprc:$RST), (ins gprc:$A, gprc:$B),
"lhzcix $RST, $A, $B", IIC_LdStLoad, []>;
def LWZCIX : XForm_base_r3xo<31, 789, (outs gprc:$RST), (ins gprc:$A, gprc:$B),
"lwzcix $RST, $A, $B", IIC_LdStLoad, []>;
def LDCIX : XForm_base_r3xo<31, 885, (outs gprc:$RST), (ins gprc:$A, gprc:$B),
"ldcix $RST, $A, $B", IIC_LdStLoad, []>;
def STBCIX : XForm_base_r3xo<31, 981, (outs), (ins gprc:$RST, gprc:$A, gprc:$B),
"stbcix $RST, $A, $B", IIC_LdStLoad, []>;
def STHCIX : XForm_base_r3xo<31, 949, (outs), (ins gprc:$RST, gprc:$A, gprc:$B),
"sthcix $RST, $A, $B", IIC_LdStLoad, []>;
def STWCIX : XForm_base_r3xo<31, 917, (outs), (ins gprc:$RST, gprc:$A, gprc:$B),
"stwcix $RST, $A, $B", IIC_LdStLoad, []>;
def STDCIX : XForm_base_r3xo<31, 1013, (outs), (ins gprc:$RST, gprc:$A, gprc:$B),
"stdcix $RST, $A, $B", IIC_LdStLoad, []>;
//===----------------------------------------------------------------------===//
// PowerPC Assembler Instruction Aliases
//

17
test/MC/Disassembler/PowerPC/ppc64-encoding-ext.txt
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@ -2275,6 +2275,23 @@
# CHECK: rfid
0x4c 0x00 0x00 0x24
# CHECK: lbzcix 21, 5, 7
0x7e 0xa5 0x3e 0xaa
# CHECK: lhzcix 21, 5, 7
0x7e 0xa5 0x3e 0x6a
# CHECK: lwzcix 21, 5, 7
0x7e 0xa5 0x3e 0x2a
# CHECK: ldcix 21, 5, 7
0x7e 0xa5 0x3e 0xea
# CHECK: stbcix 21, 5, 7
0x7e 0xa5 0x3f 0xaa
# CHECK: sthcix 21, 5, 7
0x7e 0xa5 0x3f 0x6a
# CHECK: stwcix 21, 5, 7
0x7e 0xa5 0x3f 0x2a
# CHECK: stdcix 21, 5, 7
0x7e 0xa5 0x3f 0xea
# CHECK: attn
0x00 0x00 0x02 0x00

27
test/MC/PowerPC/ppc64-encoding-ext.s
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@ -3634,6 +3634,33 @@
# CHECK-LE: mtspr 280, 2 # encoding: [0xa6,0x43,0x58,0x7c]
mtasr 2
# Load and Store Caching Inhibited Instructions
# CHECK-BE: lbzcix 21, 5, 7 # encoding: [0x7e,0xa5,0x3e,0xaa]
# CHECK-LE: lbzcix 21, 5, 7 # encoding: [0xaa,0x3e,0xa5,0x7e]
lbzcix 21, 5, 7
# CHECK-BE: lhzcix 21, 5, 7 # encoding: [0x7e,0xa5,0x3e,0x6a]
# CHECK-LE: lhzcix 21, 5, 7 # encoding: [0x6a,0x3e,0xa5,0x7e]
lhzcix 21, 5, 7
# CHECK-BE: lwzcix 21, 5, 7 # encoding: [0x7e,0xa5,0x3e,0x2a]
# CHECK-LE: lwzcix 21, 5, 7 # encoding: [0x2a,0x3e,0xa5,0x7e]
lwzcix 21, 5, 7
# CHECK-BE: ldcix 21, 5, 7 # encoding: [0x7e,0xa5,0x3e,0xea]
# CHECK-LE: ldcix 21, 5, 7 # encoding: [0xea,0x3e,0xa5,0x7e]
ldcix 21, 5, 7
# CHECK-BE: stbcix 21, 5, 7 # encoding: [0x7e,0xa5,0x3f,0xaa]
# CHECK-LE: stbcix 21, 5, 7 # encoding: [0xaa,0x3f,0xa5,0x7e]
stbcix 21, 5, 7
# CHECK-BE: sthcix 21, 5, 7 # encoding: [0x7e,0xa5,0x3f,0x6a]
# CHECK-LE: sthcix 21, 5, 7 # encoding: [0x6a,0x3f,0xa5,0x7e]
sthcix 21, 5, 7
# CHECK-BE: stwcix 21, 5, 7 # encoding: [0x7e,0xa5,0x3f,0x2a]
# CHECK-LE: stwcix 21, 5, 7 # encoding: [0x2a,0x3f,0xa5,0x7e]
stwcix 21, 5, 7
# CHECK-BE: stdcix 21, 5, 7 # encoding: [0x7e,0xa5,0x3f,0xea]
# CHECK-LE: stdcix 21, 5, 7 # encoding: [0xea,0x3f,0xa5,0x7e]
stdcix 21, 5, 7
# Processor-Specific Instructions
# CHECK-BE: attn # encoding: [0x00,0x00,0x02,0x00]
# CHECK-LE: attn # encoding: [0x00,0x02,0x00,0x00]