Remove the '-disable-scheduling' flag and replace it with the 'source' option of

the '-pre-RA-sched' flag. It actually makes more sense to do it this way. Also,
keep track of the SDNode ordering by default. Eventually, we would like to make
this ordering a way to break a "tie" in the scheduler. However, doing that now
breaks the "CodeGen/X86/abi-isel.ll" test for 32-bit Linux.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94308 91177308-0d34-0410-b5e6-96231b3b80d8

include/llvm/CodeGen/LinkAllCodegenComponents.h

@@ -44,6 +44,7 @@ namespace {
       
       (void) llvm::createBURRListDAGScheduler(NULL, llvm::CodeGenOpt::Default);
       (void) llvm::createTDRRListDAGScheduler(NULL, llvm::CodeGenOpt::Default);
+      (void) llvm::createSourceListDAGScheduler(NULL,llvm::CodeGenOpt::Default);
       (void) llvm::createTDListDAGScheduler(NULL, llvm::CodeGenOpt::Default);
       (void) llvm::createFastDAGScheduler(NULL, llvm::CodeGenOpt::Default);
       (void) llvm::createDefaultScheduler(NULL, llvm::CodeGenOpt::Default);

include/llvm/CodeGen/SchedulerRegistry.h

@@ -73,6 +73,11 @@ ScheduleDAGSDNodes *createBURRListDAGScheduler(SelectionDAGISel *IS,
 ScheduleDAGSDNodes *createTDRRListDAGScheduler(SelectionDAGISel *IS,
                                                CodeGenOpt::Level OptLevel);
 
+/// createBURRListDAGScheduler - This creates a bottom up register usage
+/// reduction list scheduler that schedules in source code order when possible.
+ScheduleDAGSDNodes *createSourceListDAGScheduler(SelectionDAGISel *IS,
+                                                 CodeGenOpt::Level OptLevel);
+
 /// createTDListDAGScheduler - This creates a top-down list scheduler with
 /// a hazard recognizer.
 ScheduleDAGSDNodes *createTDListDAGScheduler(SelectionDAGISel *IS,

lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp

@@ -46,6 +46,11 @@ static RegisterScheduler
   tdrListrDAGScheduler("list-tdrr",
                        "Top-down register reduction list scheduling",
                        createTDRRListDAGScheduler);
+static RegisterScheduler
+  sourceListDAGScheduler("source",
+                         "Similar to list-burr but schedules in source "
+                         "order when possible",
+                         createSourceListDAGScheduler);
 
 namespace {
 //===----------------------------------------------------------------------===//
@@ -931,6 +936,16 @@ namespace {
     
     bool operator()(const SUnit* left, const SUnit* right) const;
   };
+
+  struct src_ls_rr_sort : public std::binary_function<SUnit*, SUnit*, bool> {
+    RegReductionPriorityQueue<src_ls_rr_sort> *SPQ;
+    src_ls_rr_sort(RegReductionPriorityQueue<src_ls_rr_sort> *spq)
+      : SPQ(spq) {}
+    src_ls_rr_sort(const src_ls_rr_sort &RHS)
+      : SPQ(RHS.SPQ) {}
+    
+    bool operator()(const SUnit* left, const SUnit* right) const;
+  };
 }  // end anonymous namespace
 
 /// CalcNodeSethiUllmanNumber - Compute Sethi Ullman number.
@@ -981,9 +996,9 @@ namespace {
 
   public:
     RegReductionPriorityQueue(const TargetInstrInfo *tii,
-                              const TargetRegisterInfo *tri) :
+                              const TargetRegisterInfo *tri)
-    Queue(SF(this)), currentQueueId(0),
+      : Queue(SF(this)), currentQueueId(0),
-    TII(tii), TRI(tri), scheduleDAG(NULL) {}
+        TII(tii), TRI(tri), scheduleDAG(NULL) {}
     
     void initNodes(std::vector<SUnit> &sunits) {
       SUnits = &sunits;
@@ -1089,6 +1104,9 @@ namespace {
 
   typedef RegReductionPriorityQueue<td_ls_rr_sort>
     TDRegReductionPriorityQueue;
+
+  typedef RegReductionPriorityQueue<src_ls_rr_sort>
+    SrcRegReductionPriorityQueue;
 }
 
 /// closestSucc - Returns the scheduled cycle of the successor which is
@@ -1122,16 +1140,9 @@ static unsigned calcMaxScratches(const SUnit *SU) {
   return Scratches;
 }
 
-// Bottom up
+template <typename RRSort>
-bool bu_ls_rr_sort::operator()(const SUnit *left, const SUnit *right) const {
+static bool BURRSort(const SUnit *left, const SUnit *right,
-  unsigned LOrder = SPQ->getNodeOrdering(left);
+                     const RegReductionPriorityQueue<RRSort> *SPQ) {
-  unsigned ROrder = SPQ->getNodeOrdering(right);
-
-  // Prefer an ordering where the lower the non-zero order number, the higher
-  // the preference.
-  if ((LOrder || ROrder) && LOrder != ROrder)
-    return LOrder != 0 && (LOrder < ROrder || ROrder == 0);
-
   unsigned LPriority = SPQ->getNodePriority(left);
   unsigned RPriority = SPQ->getNodePriority(right);
   if (LPriority != RPriority)
@@ -1176,6 +1187,24 @@ bool bu_ls_rr_sort::operator()(const SUnit *left, const SUnit *right) const {
   return (left->NodeQueueId > right->NodeQueueId);
 }
 
+// Bottom up
+bool bu_ls_rr_sort::operator()(const SUnit *left, const SUnit *right) const {
+  return BURRSort(left, right, SPQ);
+}
+
+// Source order, otherwise bottom up.
+bool src_ls_rr_sort::operator()(const SUnit *left, const SUnit *right) const{
+  unsigned LOrder = SPQ->getNodeOrdering(left);
+  unsigned ROrder = SPQ->getNodeOrdering(right);
+
+  // Prefer an ordering where the lower the non-zero order number, the higher
+  // the preference.
+  if ((LOrder || ROrder) && LOrder != ROrder)
+    return LOrder != 0 && (LOrder < ROrder || ROrder == 0);
+
+  return BURRSort(left, right, SPQ);
+}
+
 template<class SF>
 bool
 RegReductionPriorityQueue<SF>::canClobber(const SUnit *SU, const SUnit *Op) {
@@ -1196,7 +1225,6 @@ RegReductionPriorityQueue<SF>::canClobber(const SUnit *SU, const SUnit *Op) {
   return false;
 }
 
-
 /// hasCopyToRegUse - Return true if SU has a value successor that is a
 /// CopyToReg node.
 static bool hasCopyToRegUse(const SUnit *SU) {
@@ -1544,3 +1572,17 @@ llvm::createTDRRListDAGScheduler(SelectionDAGISel *IS, CodeGenOpt::Level) {
   PQ->setScheduleDAG(SD);
   return SD;
 }
+
+llvm::ScheduleDAGSDNodes *
+llvm::createSourceListDAGScheduler(SelectionDAGISel *IS, CodeGenOpt::Level) {
+  const TargetMachine &TM = IS->TM;
+  const TargetInstrInfo *TII = TM.getInstrInfo();
+  const TargetRegisterInfo *TRI = TM.getRegisterInfo();
+  
+  SrcRegReductionPriorityQueue *PQ = new SrcRegReductionPriorityQueue(TII, TRI);
+
+  ScheduleDAGRRList *SD =
+    new ScheduleDAGRRList(*IS->MF, true, PQ);
+  PQ->setScheduleDAG(SD);
+  return SD;  
+}

lib/CodeGen/SelectionDAG/SelectionDAG.cpp

@@ -593,7 +593,7 @@ void SelectionDAG::DeallocateNode(SDNode *N) {
   NodeAllocator.Deallocate(AllNodes.remove(N));
 
   // Remove the ordering of this node.
-  if (Ordering) Ordering->remove(N);
+  Ordering->remove(N);
 }
 
 /// RemoveNodeFromCSEMaps - Take the specified node out of the CSE map that
@@ -790,8 +790,7 @@ SelectionDAG::SelectionDAG(TargetLowering &tli, FunctionLoweringInfo &fli)
               getVTList(MVT::Other)),
     Root(getEntryNode()), Ordering(0) {
   AllNodes.push_back(&EntryNode);
-  if (DisableScheduling)
+  Ordering = new SDNodeOrdering();
-    Ordering = new SDNodeOrdering();
 }
 
 void SelectionDAG::init(MachineFunction &mf, MachineModuleInfo *mmi,
@@ -830,8 +829,7 @@ void SelectionDAG::clear() {
   EntryNode.UseList = 0;
   AllNodes.push_back(&EntryNode);
   Root = getEntryNode();
-  if (DisableScheduling)
+  Ordering = new SDNodeOrdering();
-    Ordering = new SDNodeOrdering();
 }
 
 SDValue SelectionDAG::getSExtOrTrunc(SDValue Op, DebugLoc DL, EVT VT) {
@@ -5241,14 +5239,13 @@ unsigned SelectionDAG::AssignTopologicalOrder() {
 /// AssignOrdering - Assign an order to the SDNode.
 void SelectionDAG::AssignOrdering(SDNode *SD, unsigned Order) {
   assert(SD && "Trying to assign an order to a null node!");
-  if (Ordering)
+  Ordering->add(SD, Order);
-    Ordering->add(SD, Order);
 }
 
 /// GetOrdering - Get the order for the SDNode.
 unsigned SelectionDAG::GetOrdering(const SDNode *SD) const {
   assert(SD && "Trying to get the order of a null node!");
-  return Ordering ? Ordering->getOrder(SD) : 0;
+  return Ordering->getOrder(SD);
 }
 
 

lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp

@@ -144,7 +144,7 @@ namespace llvm {
     if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency)
       return createTDListDAGScheduler(IS, OptLevel);
     assert(TLI.getSchedulingPreference() ==
-         TargetLowering::SchedulingForRegPressure && "Unknown sched type!");
+           TargetLowering::SchedulingForRegPressure && "Unknown sched type!");
     return createBURRListDAGScheduler(IS, OptLevel);
   }
 }

lib/Target/TargetMachine.cpp

@@ -46,7 +46,6 @@ namespace llvm {
   bool DisableJumpTables;
   bool StrongPHIElim;
   bool AsmVerbosityDefault(false);
-  bool DisableScheduling;
 }
 
 static cl::opt<bool, true>
@@ -198,11 +197,6 @@ EnableStrongPHIElim(cl::Hidden, "strong-phi-elim",
   cl::desc("Use strong PHI elimination."),
   cl::location(StrongPHIElim),
   cl::init(false));
-static cl::opt<bool, true>
-DisableInstScheduling("disable-scheduling",
-  cl::desc("Disable instruction scheduling"),
-  cl::location(DisableScheduling),
-  cl::init(false));
 
 //---------------------------------------------------------------------------
 // TargetMachine Class