diff --git a/lib/Target/Mips/MipsRegisterInfo.td b/lib/Target/Mips/MipsRegisterInfo.td
index f2e97b6735c..0e762f23e4a 100644
--- a/lib/Target/Mips/MipsRegisterInfo.td
+++ b/lib/Target/Mips/MipsRegisterInfo.td
@@ -174,7 +174,7 @@ let Namespace = "Mips" in {
   /// Mips MSA registers
   /// MSA and FPU cannot both be present unless the FPU has 64-bit registers
   foreach I = 0-31 in
-  def W#I : AFPR128<0, "w"#I, [!cast<AFPR64>("D"#I#"_64")]>,
+  def W#I : AFPR128<I, "w"#I, [!cast<AFPR64>("D"#I#"_64")]>,
             DwarfRegNum<[!add(I, 32)]>;
 
   // Hi/Lo registers