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https://github.com/c64scene-ar/llvm-6502.git
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Implement LowerCall_64 for the SPARC v9 64-bit ABI.
There is still no support for byval arguments (which I don't think are needed) and varargs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178993 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen
parent
0f08eb1359
commit
18fdb398ea
@ -594,6 +594,15 @@ LowerFormalArguments_64(SDValue Chain,
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SDValue
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SparcTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
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SmallVectorImpl<SDValue> &InVals) const {
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if (Subtarget->is64Bit())
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return LowerCall_64(CLI, InVals);
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return LowerCall_32(CLI, InVals);
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}
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// Lower a call for the 32-bit ABI.
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SDValue
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SparcTargetLowering::LowerCall_32(TargetLowering::CallLoweringInfo &CLI,
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SmallVectorImpl<SDValue> &InVals) const {
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SelectionDAG &DAG = CLI.DAG;
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DebugLoc &dl = CLI.DL;
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SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs;
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@ -887,6 +896,221 @@ SparcTargetLowering::getSRetArgSize(SelectionDAG &DAG, SDValue Callee) const
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return getDataLayout()->getTypeAllocSize(ElementTy);
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}
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// Lower a call for the 64-bit ABI.
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SDValue
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SparcTargetLowering::LowerCall_64(TargetLowering::CallLoweringInfo &CLI,
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SmallVectorImpl<SDValue> &InVals) const {
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SelectionDAG &DAG = CLI.DAG;
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DebugLoc DL = CLI.DL;
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SDValue Chain = CLI.Chain;
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// Analyze operands of the call, assigning locations to each operand.
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SmallVector<CCValAssign, 16> ArgLocs;
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CCState CCInfo(CLI.CallConv, CLI.IsVarArg, DAG.getMachineFunction(),
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DAG.getTarget(), ArgLocs, *DAG.getContext());
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CCInfo.AnalyzeCallOperands(CLI.Outs, CC_Sparc64);
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// Get the size of the outgoing arguments stack space requirement.
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// The stack offset computed by CC_Sparc64 includes all arguments.
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// We always allocate space for 6 arguments in the prolog.
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unsigned ArgsSize = std::max(6*8u, CCInfo.getNextStackOffset()) - 6*8u;
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// Keep stack frames 16-byte aligned.
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ArgsSize = RoundUpToAlignment(ArgsSize, 16);
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// Adjust the stack pointer to make room for the arguments.
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// FIXME: Use hasReservedCallFrame to avoid %sp adjustments around all calls
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// with more than 6 arguments.
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Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(ArgsSize, true));
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// Collect the set of registers to pass to the function and their values.
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// This will be emitted as a sequence of CopyToReg nodes glued to the call
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// instruction.
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SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
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// Collect chains from all the memory opeations that copy arguments to the
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// stack. They must follow the stack pointer adjustment above and precede the
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// call instruction itself.
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SmallVector<SDValue, 8> MemOpChains;
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for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
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const CCValAssign &VA = ArgLocs[i];
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SDValue Arg = CLI.OutVals[i];
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// Promote the value if needed.
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switch (VA.getLocInfo()) {
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default:
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llvm_unreachable("Unknown location info!");
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case CCValAssign::Full:
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break;
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case CCValAssign::SExt:
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Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Arg);
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break;
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case CCValAssign::ZExt:
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Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg);
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break;
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case CCValAssign::AExt:
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Arg = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Arg);
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break;
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case CCValAssign::BCvt:
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Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg);
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break;
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}
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if (VA.isRegLoc()) {
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// The custom bit on an i32 return value indicates that it should be
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// passed in the high bits of the register.
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if (VA.getValVT() == MVT::i32 && VA.needsCustom()) {
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Arg = DAG.getNode(ISD::SHL, DL, MVT::i64, Arg,
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DAG.getConstant(32, MVT::i32));
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// The next value may go in the low bits of the same register.
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// Handle both at once.
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if (i+1 < ArgLocs.size() && ArgLocs[i+1].isRegLoc() &&
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ArgLocs[i+1].getLocReg() == VA.getLocReg()) {
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SDValue NV = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64,
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CLI.OutVals[i+1]);
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Arg = DAG.getNode(ISD::OR, DL, MVT::i64, Arg, NV);
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// Skip the next value, it's already done.
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++i;
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}
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}
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// The argument registers are described in term of the callee's register
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// window, so translate I0-I7 -> O0-O7.
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unsigned Reg = VA.getLocReg();
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if (Reg >= SP::I0 && Reg <= SP::I7)
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Reg = Reg - SP::I0 + SP::O0;
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RegsToPass.push_back(std::make_pair(Reg, Arg));
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continue;
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}
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assert(VA.isMemLoc());
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// Create a store off the stack pointer for this argument.
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SDValue StackPtr = DAG.getRegister(SP::O6, getPointerTy());
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// The argument area starts at %fp+BIAS+128 in the callee frame,
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// %sp+BIAS+128 in ours.
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SDValue PtrOff = DAG.getIntPtrConstant(VA.getLocMemOffset() +
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Subtarget->getStackPointerBias() +
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128);
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PtrOff = DAG.getNode(ISD::ADD, DL, getPointerTy(), StackPtr, PtrOff);
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MemOpChains.push_back(DAG.getStore(Chain, DL, Arg, PtrOff,
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MachinePointerInfo(),
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false, false, 0));
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}
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// Emit all stores, make sure they occur before the call.
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if (!MemOpChains.empty())
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Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
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&MemOpChains[0], MemOpChains.size());
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// Build a sequence of CopyToReg nodes glued together with token chain and
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// glue operands which copy the outgoing args into registers. The InGlue is
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// necessary since all emitted instructions must be stuck together in order
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// to pass the live physical registers.
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SDValue InGlue;
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for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
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Chain = DAG.getCopyToReg(Chain, DL,
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RegsToPass[i].first, RegsToPass[i].second, InGlue);
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InGlue = Chain.getValue(1);
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}
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// If the callee is a GlobalAddress node (quite common, every direct call is)
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// turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
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// Likewise ExternalSymbol -> TargetExternalSymbol.
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SDValue Callee = CLI.Callee;
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if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
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Callee = DAG.getTargetGlobalAddress(G->getGlobal(), DL, getPointerTy());
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else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
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Callee = DAG.getTargetExternalSymbol(E->getSymbol(), getPointerTy());
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// Build the operands for the call instruction itself.
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SmallVector<SDValue, 8> Ops;
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Ops.push_back(Chain);
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Ops.push_back(Callee);
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for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
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Ops.push_back(DAG.getRegister(RegsToPass[i].first,
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RegsToPass[i].second.getValueType()));
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// Make sure the CopyToReg nodes are glued to the call instruction which
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// consumes the registers.
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if (InGlue.getNode())
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Ops.push_back(InGlue);
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// Now the call itself.
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SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
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Chain = DAG.getNode(SPISD::CALL, DL, NodeTys, &Ops[0], Ops.size());
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InGlue = Chain.getValue(1);
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// Revert the stack pointer immediately after the call.
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Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(ArgsSize, true),
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DAG.getIntPtrConstant(0, true), InGlue);
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InGlue = Chain.getValue(1);
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// Now extract the return values. This is more or less the same as
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// LowerFormalArguments_64.
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// Assign locations to each value returned by this call.
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SmallVector<CCValAssign, 16> RVLocs;
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CCState RVInfo(CLI.CallConv, CLI.IsVarArg, DAG.getMachineFunction(),
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DAG.getTarget(), RVLocs, *DAG.getContext());
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RVInfo.AnalyzeCallResult(CLI.Ins, CC_Sparc64);
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// Copy all of the result registers out of their specified physreg.
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for (unsigned i = 0; i != RVLocs.size(); ++i) {
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CCValAssign &VA = RVLocs[i];
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unsigned Reg = VA.getLocReg();
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// Remap I0-I7 -> O0-O7.
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if (Reg >= SP::I0 && Reg <= SP::I7)
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Reg = Reg - SP::I0 + SP::O0;
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// When returning 'inreg {i32, i32 }', two consecutive i32 arguments can
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// reside in the same register in the high and low bits. Reuse the
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// CopyFromReg previous node to avoid duplicate copies.
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SDValue RV;
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if (RegisterSDNode *SrcReg = dyn_cast<RegisterSDNode>(Chain.getOperand(1)))
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if (SrcReg->getReg() == Reg && Chain->getOpcode() == ISD::CopyFromReg)
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RV = Chain.getValue(0);
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// But usually we'll create a new CopyFromReg for a different register.
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if (!RV.getNode()) {
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RV = DAG.getCopyFromReg(Chain, DL, Reg, RVLocs[i].getLocVT(), InGlue);
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Chain = RV.getValue(1);
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InGlue = Chain.getValue(2);
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}
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// Get the high bits for i32 struct elements.
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if (VA.getValVT() == MVT::i32 && VA.needsCustom())
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RV = DAG.getNode(ISD::SRL, DL, VA.getLocVT(), RV,
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DAG.getConstant(32, MVT::i32));
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// The callee promoted the return value, so insert an Assert?ext SDNode so
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// we won't promote the value again in this function.
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switch (VA.getLocInfo()) {
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case CCValAssign::SExt:
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RV = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), RV,
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DAG.getValueType(VA.getValVT()));
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break;
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case CCValAssign::ZExt:
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RV = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), RV,
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DAG.getValueType(VA.getValVT()));
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break;
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default:
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break;
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}
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// Truncate the register down to the return value type.
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if (VA.isExtInLoc())
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RV = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), RV);
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InVals.push_back(RV);
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}
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return Chain;
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}
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//===----------------------------------------------------------------------===//
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// TargetLowering Implementation
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//===----------------------------------------------------------------------===//
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@ -95,6 +95,10 @@ namespace llvm {
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virtual SDValue
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LowerCall(TargetLowering::CallLoweringInfo &CLI,
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SmallVectorImpl<SDValue> &InVals) const;
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SDValue LowerCall_32(TargetLowering::CallLoweringInfo &CLI,
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SmallVectorImpl<SDValue> &InVals) const;
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SDValue LowerCall_64(TargetLowering::CallLoweringInfo &CLI,
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SmallVectorImpl<SDValue> &InVals) const;
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virtual SDValue
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LowerReturn(SDValue Chain,
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@ -1,4 +1,4 @@
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; RUN: llc < %s -march=sparcv9 | FileCheck %s
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; RUN: llc < %s -march=sparcv9 -disable-sparc-delay-filler | FileCheck %s
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; CHECK: intarg
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; CHECK: stb %i0, [%i4]
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@ -17,7 +17,7 @@ define void @intarg(i8 %a0, ; %i0
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i32 %a3, ; %i3
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i8* %a4, ; %i4
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i32 %a5, ; %i5
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i32 %a6, ; [%fp+BIAS+176]
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i32 signext %a6, ; [%fp+BIAS+176]
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i8* %a7) { ; [%fp+BIAS+184]
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store i8 %a0, i8* %a4
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store i8 %a1, i8* %a4
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@ -33,6 +33,18 @@ define void @intarg(i8 %a0, ; %i0
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ret void
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}
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; CHECK: call_intarg
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; Sign-extend and store the full 64 bits.
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; CHECK: sra %i0, 0, [[R:%[gilo][0-7]]]
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; CHECK: stx [[R]], [%sp+2223]
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; Use %o0-%o5 for outgoing arguments
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; CHECK: or %g0, 5, %o5
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; CHECK: call intarg
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define void @call_intarg(i32 %i0, i8* %i1) {
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call void @intarg(i8 0, i8 1, i16 2, i32 3, i8* undef, i32 5, i32 %i0, i8* %i1)
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ret void
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}
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; CHECK: floatarg
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; CHECK: fstod %f1,
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; CHECK: faddd %f2,
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@ -57,7 +69,7 @@ define double @floatarg(float %a0, ; %f1
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float %a14, ; %f29
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float %a15, ; %f31
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float %a16, ; [%fp+BIAS+256] (using 8 bytes)
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float %a17) { ; [%fp+BIAS+264] (using 8 bytes)
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double %a17) { ; [%fp+BIAS+264] (using 8 bytes)
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%d0 = fpext float %a0 to double
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%s1 = fadd double %a1, %d0
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%s2 = fadd double %a2, %s1
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@ -68,6 +80,23 @@ define double @floatarg(float %a0, ; %f1
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ret double %s17
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}
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; CHECK: call_floatarg
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; Store 4 bytes, right-aligned in slot.
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; CHECK: st %f1, [%sp+2307]
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; Store 8 bytes in full slot.
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; CHECK: std %f2, [%sp+2311]
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; CHECK: fmovd %f2, %f4
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; CHECK: call floatarg
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define void @call_floatarg(float %f1, double %d2, float %f5, double *%p) {
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%r = call double @floatarg(float %f5, double %d2, double %d2, double %d2,
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float %f5, float %f5, float %f5, float %f5,
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float %f5, float %f5, float %f5, float %f5,
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float %f5, float %f5, float %f5, float %f5,
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float %f1, double %d2)
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store double %r, double* %p
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ret void
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}
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; CHECK: mixedarg
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; CHECK: fstod %f3
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; CHECK: faddd %f6
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@ -92,6 +121,26 @@ define void @mixedarg(i8 %a0, ; %i0
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ret void
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}
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; CHECK: call_mixedarg
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; CHECK: stx %i2, [%sp+2247]
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; CHECK: stx %i0, [%sp+2223]
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; CHECK: fmovd %f2, %f6
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; CHECK: fmovd %f2, %f16
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; CHECK: call mixedarg
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define void @call_mixedarg(i64 %i0, double %f2, i16* %i2) {
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call void @mixedarg(i8 undef,
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float undef,
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i16 undef,
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double %f2,
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i13 undef,
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float undef,
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i64 %i0,
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double* undef,
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double %f2,
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i16* %i2)
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ret void
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}
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; The inreg attribute is used to indicate 32-bit sized struct elements that
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; share an 8-byte slot.
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; CHECK: inreg_fi
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@ -105,6 +154,15 @@ define i32 @inreg_fi(i32 inreg %a0, ; high bits of %i0
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ret i32 %rv
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}
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; CHECK: call_inreg_fi
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; CHECK: sllx %i1, 32, %o0
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; CHECK: fmovs %f5, %f1
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; CHECK: call inreg_fi
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define void @call_inreg_fi(i32* %p, i32 %i1, float %f5) {
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%x = call i32 @inreg_fi(i32 %i1, float %f5)
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ret void
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}
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; CHECK: inreg_ff
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; CHECK: fsubs %f0, %f1, %f1
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define float @inreg_ff(float inreg %a0, ; %f0
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@ -113,6 +171,15 @@ define float @inreg_ff(float inreg %a0, ; %f0
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ret float %rv
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}
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; CHECK: call_inreg_ff
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; CHECK: fmovs %f3, %f0
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; CHECK: fmovs %f5, %f1
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; CHECK: call inreg_ff
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define void @call_inreg_ff(i32* %p, float %f3, float %f5) {
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%x = call float @inreg_ff(float %f3, float %f5)
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ret void
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}
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; CHECK: inreg_if
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; CHECK: fstoi %f0
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; CHECK: sub %i0
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@ -123,6 +190,15 @@ define i32 @inreg_if(float inreg %a0, ; %f0
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ret i32 %rv
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}
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; CHECK: call_inreg_if
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; CHECK: fmovs %f3, %f0
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; CHECK: or %g0, %i2, %o0
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; CHECK: call inreg_if
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define void @call_inreg_if(i32* %p, float %f3, i32 %i2) {
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%x = call i32 @inreg_if(float %f3, i32 %i2)
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ret void
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}
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; The frontend shouldn't do this. Just pass i64 instead.
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; CHECK: inreg_ii
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; CHECK: srlx %i0, 32, [[R:%[gilo][0-7]]]
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@ -133,6 +209,16 @@ define i32 @inreg_ii(i32 inreg %a0, ; high bits of %i0
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ret i32 %rv
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}
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; CHECK: call_inreg_ii
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; CHECK: srl %i2, 0, [[R2:%[gilo][0-7]]]
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; CHECK: sllx %i1, 32, [[R1:%[gilo][0-7]]]
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; CHECK: or [[R1]], [[R2]], %o0
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; CHECK: call inreg_ii
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define void @call_inreg_ii(i32* %p, i32 %i1, i32 %i2) {
|
||||
%x = call i32 @inreg_ii(i32 %i1, i32 %i2)
|
||||
ret void
|
||||
}
|
||||
|
||||
; Structs up to 32 bytes in size can be returned in registers.
|
||||
; CHECK: ret_i64_pair
|
||||
; CHECK: ldx [%i2], %i0
|
||||
@ -146,6 +232,20 @@ define { i64, i64 } @ret_i64_pair(i32 %a0, i32 %a1, i64* %p, i64* %q) {
|
||||
ret { i64, i64 } %rv2
|
||||
}
|
||||
|
||||
; CHECK: call_ret_i64_pair
|
||||
; CHECK: call ret_i64_pair
|
||||
; CHECK: stx %o0, [%i0]
|
||||
; CHECK: stx %o1, [%i0]
|
||||
define void @call_ret_i64_pair(i64* %i0) {
|
||||
%rv = call { i64, i64 } @ret_i64_pair(i32 undef, i32 undef,
|
||||
i64* undef, i64* undef)
|
||||
%e0 = extractvalue { i64, i64 } %rv, 0
|
||||
store i64 %e0, i64* %i0
|
||||
%e1 = extractvalue { i64, i64 } %rv, 1
|
||||
store i64 %e1, i64* %i0
|
||||
ret void
|
||||
}
|
||||
|
||||
; This is not a C struct, each member uses 8 bytes.
|
||||
; CHECK: ret_i32_float_pair
|
||||
; CHECK: ld [%i2], %i0
|
||||
@ -160,6 +260,20 @@ define { i32, float } @ret_i32_float_pair(i32 %a0, i32 %a1,
|
||||
ret { i32, float } %rv2
|
||||
}
|
||||
|
||||
; CHECK: call_ret_i32_float_pair
|
||||
; CHECK: call ret_i32_float_pair
|
||||
; CHECK: st %o0, [%i0]
|
||||
; CHECK: st %f3, [%i1]
|
||||
define void @call_ret_i32_float_pair(i32* %i0, float* %i1) {
|
||||
%rv = call { i32, float } @ret_i32_float_pair(i32 undef, i32 undef,
|
||||
i32* undef, float* undef)
|
||||
%e0 = extractvalue { i32, float } %rv, 0
|
||||
store i32 %e0, i32* %i0
|
||||
%e1 = extractvalue { i32, float } %rv, 1
|
||||
store float %e1, float* %i1
|
||||
ret void
|
||||
}
|
||||
|
||||
; This is a C struct, each member uses 4 bytes.
|
||||
; CHECK: ret_i32_float_packed
|
||||
; CHECK: ld [%i2], [[R:%[gilo][0-7]]]
|
||||
@ -175,6 +289,21 @@ define inreg { i32, float } @ret_i32_float_packed(i32 %a0, i32 %a1,
|
||||
ret { i32, float } %rv2
|
||||
}
|
||||
|
||||
; CHECK: call_ret_i32_float_packed
|
||||
; CHECK: call ret_i32_float_packed
|
||||
; CHECK: srlx %o0, 32, [[R:%[gilo][0-7]]]
|
||||
; CHECK: st [[R]], [%i0]
|
||||
; CHECK: st %f1, [%i1]
|
||||
define void @call_ret_i32_float_packed(i32* %i0, float* %i1) {
|
||||
%rv = call { i32, float } @ret_i32_float_packed(i32 undef, i32 undef,
|
||||
i32* undef, float* undef)
|
||||
%e0 = extractvalue { i32, float } %rv, 0
|
||||
store i32 %e0, i32* %i0
|
||||
%e1 = extractvalue { i32, float } %rv, 1
|
||||
store float %e1, float* %i1
|
||||
ret void
|
||||
}
|
||||
|
||||
; The C frontend should use i64 to return { i32, i32 } structs, but verify that
|
||||
; we don't miscompile thi case where both struct elements are placed in %i0.
|
||||
; CHECK: ret_i32_packed
|
||||
@ -192,6 +321,21 @@ define inreg { i32, i32 } @ret_i32_packed(i32 %a0, i32 %a1,
|
||||
ret { i32, i32 } %rv2
|
||||
}
|
||||
|
||||
; CHECK: call_ret_i32_packed
|
||||
; CHECK: call ret_i32_packed
|
||||
; CHECK: srlx %o0, 32, [[R:%[gilo][0-7]]]
|
||||
; CHECK: st [[R]], [%i0]
|
||||
; CHECK: st %o0, [%i1]
|
||||
define void @call_ret_i32_packed(i32* %i0, i32* %i1) {
|
||||
%rv = call { i32, i32 } @ret_i32_packed(i32 undef, i32 undef,
|
||||
i32* undef, i32* undef)
|
||||
%e0 = extractvalue { i32, i32 } %rv, 0
|
||||
store i32 %e0, i32* %i0
|
||||
%e1 = extractvalue { i32, i32 } %rv, 1
|
||||
store i32 %e1, i32* %i1
|
||||
ret void
|
||||
}
|
||||
|
||||
; The return value must be sign-extended to 64 bits.
|
||||
; CHECK: ret_sext
|
||||
; CHECK: sra %i0, 0, %i0
|
||||
|
||||
Loading…
Reference in New Issue
Block a user