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Fix malformed assert.
If anybody has strong feelings about 'default: assert(0 && "blah")' vs 'default: llvm_unreachable("blah")', feel free to regularize the instances of each in this file. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147459 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -6192,7 +6192,7 @@ processInstruction(MCInst &Inst,
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ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(3).getImm());
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if (SOpc == ARM_AM::rrx) return false;
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switch (Inst.getOpcode()) {
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default: assert("unexpected opcode!");
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default: assert(0 && "unexpected opcode!");
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case ARM::ANDrsi: newOpc = ARM::ANDrr; break;
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case ARM::ORRrsi: newOpc = ARM::ORRrr; break;
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case ARM::EORrsi: newOpc = ARM::EORrr; break;
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