6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-02-02 09:33:59 +00:00
Code Issues Projects Releases Wiki Activity

Thumb2 assembly parsing and encoding for RSB.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139839 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach 2011-09-15 20:54:14 +00:00
parent 101b1c5ff1
commit 191d33fd6d
2 changed files with 40 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
lib/Target/ARM/ARMInstrThumb2.td
View File

@ -3845,3 +3845,16 @@ def : t2InstAlias<"pop${p} $regs", (t2LDMIA_UPD SP, pred:$p, reglist:$regs)>;
def : t2InstAlias<"rev${p} $Rd, $Rm", (t2REV rGPR:$Rd, rGPR:$Rm, pred:$p)>;
def : t2InstAlias<"rev16${p} $Rd, $Rm", (t2REV16 rGPR:$Rd, rGPR:$Rm, pred:$p)>;
def : t2InstAlias<"revsh${p} $Rd, $Rm", (t2REVSH rGPR:$Rd, rGPR:$Rm, pred:$p)>;
// Alias for RSB without the ".w" optional width specifier, and with optional
// implied destination register.
def : t2InstAlias<"rsb${s}${p} $Rd, $Rn, $imm",
(t2RSBri rGPR:$Rd, rGPR:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
def : t2InstAlias<"rsb${s}${p} $Rdn, $imm",
(t2RSBri rGPR:$Rdn, rGPR:$Rdn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
def : t2InstAlias<"rsb${s}${p} $Rdn, $Rm",
(t2RSBrr rGPR:$Rdn, rGPR:$Rdn, rGPR:$Rm, pred:$p, cc_out:$s)>;
def : t2InstAlias<"rsb${s}${p} $Rdn, $ShiftedRm",
(t2RSBrs rGPR:$Rdn, rGPR:$Rdn, t2_so_reg:$ShiftedRm, pred:$p,
cc_out:$s)>;

27
test/MC/ARM/basic-thumb2-instructions.s
View File

@ -1526,6 +1526,33 @@ _func:
@ CHECK: rrxlt r9, r12 @ encoding: [0x4f,0xea,0x3c,0x09]
@ CHECK: rrxsge r8, r3 @ encoding: [0x5f,0xea,0x33,0x08]
@------------------------------------------------------------------------------
@ RSB (immediate)
@------------------------------------------------------------------------------
rsb r2, r5, #0xff000
rsbs r3, r12, #0xf
rsb r1, #0xff
rsb r1, r1, #0xff
@ CHECK: rsb.w r2, r5, #1044480 @ encoding: [0xc5,0xf5,0x7f,0x22]
@ CHECK: rsbs.w r3, r12, #15 @ encoding: [0xdc,0xf1,0x0f,0x03]
@ CHECK: rsb.w r1, r1, #255 @ encoding: [0xc1,0xf1,0xff,0x01]
@ CHECK: rsb.w r1, r1, #255 @ encoding: [0xc1,0xf1,0xff,0x01]
@------------------------------------------------------------------------------
@ RSB (register)
@------------------------------------------------------------------------------
rsb r4, r8
rsb r4, r9, r8
rsb r1, r4, r8, asr #3
rsbs r2, r1, r7, lsl #1
@ CHECK: rsb r4, r4, r8 @ encoding: [0xc4,0xeb,0x08,0x04]
@ CHECK: rsb r4, r9, r8 @ encoding: [0xc9,0xeb,0x08,0x04]
@ CHECK: rsb r1, r4, r8, asr #3 @ encoding: [0xc4,0xeb,0xe8,0x01]
@ CHECK: rsbs r2, r1, r7, lsl #1 @ encoding: [0xd1,0xeb,0x47,0x02]
@------------------------------------------------------------------------------
@ SUB (register)