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Enable prefetch generation on PPC64.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153851 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Hal Finkel 2012-04-01 20:08:17 +00:00
parent 730acfb413
commit 19aa2b5015
3 changed files with 21 additions and 0 deletions
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3
lib/Target/PowerPC/PPCISelLowering.cpp
View File

@ -389,6 +389,9 @@ PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
}
if (TM.getSubtarget<PPCSubtarget>().has64BitSupport())
setOperationAction(ISD::PREFETCH, MVT::Other, Legal);
setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Expand);
setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Expand);

3
lib/Target/PowerPC/PPCInstrInfo.td
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@ -545,6 +545,9 @@ def DCBZL : DCB_Form<1014, 1, (outs), (ins memrr:$dst),
"dcbzl $dst", LdStDCBF, [(int_ppc_dcbzl xoaddr:$dst)]>,
PPC970_DGroup_Single;
def : Pat<(prefetch xoaddr:$dst, (i32 0), imm, (i32 1)),
(DCBT xoaddr:$dst)>;
// Atomic operations
let usesCustomInserter = 1 in {
let Defs = [CR0] in {

15
test/CodeGen/PowerPC/ppc64-prefetch.ll Normal file
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@ -0,0 +1,15 @@
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64"
target triple = "powerpc64-unknown-linux-gnu"
; RUN: llc < %s | FileCheck %s
define void @test1(i8* %a, ...) nounwind {
entry:
call void @llvm.prefetch(i8* %a, i32 0, i32 3, i32 1)
ret void
}
declare void @llvm.prefetch(i8*, i32, i32, i32)
; CHECK: @test1
; CHECK: dcbt