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For double-spaced VLD3/VLD4 instructions, copy the explicit super-register use

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operand from the pseudo instruction to the new instruction as an implicit use.
This will preserve any other flags (e.g., kill) on the operand.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113456 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bob Wilson 2010-09-09 00:38:32 +00:00
parent 4620360842
commit 19d644d5a9
1 changed files with 9 additions and 5 deletions
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14
lib/Target/ARM/ARMExpandPseudoInsts.cpp
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@ -122,13 +122,17 @@ void ARMExpandPseudo::ExpandVLD(MachineBasicBlock::iterator &MBBI,
MIB.addOperand(MI.getOperand(OpIdx++)); MIB.addOperand(MI.getOperand(OpIdx++));
MIB = AddDefaultPred(MIB); MIB = AddDefaultPred(MIB);
TransferImpOps(MI, MIB, MIB); // For an instruction writing double-spaced subregs, the pseudo instruction
// For an instruction writing the odd subregs, add an implicit use of the // has an extra operand that is a use of the super-register. Copy that over
// super-register because the even subregs were loaded separately. // to the new instruction as an implicit operand.
if (RegSpc == EvenDblSpc || RegSpc == OddDblSpc) if (RegSpc == EvenDblSpc || RegSpc == OddDblSpc) {
MIB.addReg(DstReg, RegState::Implicit); MachineOperand MO = MI.getOperand(OpIdx);
MO.setImplicit(true);
MIB.addOperand(MO);
}
// Add an implicit def for the super-register. // Add an implicit def for the super-register.
MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));
TransferImpOps(MI, MIB, MIB);
MI.eraseFromParent(); MI.eraseFromParent();
} }