Fix crashing on invalid inline asm with matching constraints.

For a testcase like the following:

 typedef unsigned long uint64_t;

 typedef struct {
   uint64_t lo;
   uint64_t hi;
 } blob128_t;

 void add_128_to_128(const blob128_t *in, blob128_t *res) {
   asm ("PAND %1, %0" : "+Q"(*res) : "Q"(*in));
 }

where we'll fail to allocate the register for the output constraint,
our matching input constraint will not find a register to match,
and could try to search past the end of the current operands array.

On the idea that we'd like to attempt to keep compilation going
to find more errors in the module, change the error cases when
we're visiting inline asm IR to return immediately and avoid
trying to create a node in the DAG. This leaves us with only
a single error message per inline asm instruction, but allows us
to safely keep going in the general case.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187470 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Eric Christopher 2013-07-31 01:26:24 +00:00
parent 782638aa0d
commit 1a54c57cf6

View File

@ -6129,7 +6129,7 @@ void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) {
Ctx.emitError(CS.getInstruction(), Ctx.emitError(CS.getInstruction(),
"couldn't allocate output register for constraint '" + "couldn't allocate output register for constraint '" +
Twine(OpInfo.ConstraintCode) + "'"); Twine(OpInfo.ConstraintCode) + "'");
break; return;
} }
// If this is an indirect operand, store through the pointer after the // If this is an indirect operand, store through the pointer after the
@ -6185,7 +6185,7 @@ void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) {
Ctx.emitError(CS.getInstruction(), "inline asm not supported yet:" Ctx.emitError(CS.getInstruction(), "inline asm not supported yet:"
" don't know how to handle tied " " don't know how to handle tied "
"indirect register inputs"); "indirect register inputs");
report_fatal_error("Cannot handle indirect register inputs!"); return;
} }
RegsForValue MatchedRegs; RegsForValue MatchedRegs;
@ -6199,10 +6199,10 @@ void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) {
MatchedRegs.Regs.push_back(RegInfo.createVirtualRegister(RC)); MatchedRegs.Regs.push_back(RegInfo.createVirtualRegister(RC));
else { else {
LLVMContext &Ctx = *DAG.getContext(); LLVMContext &Ctx = *DAG.getContext();
Ctx.emitError(CS.getInstruction(), "inline asm error: This value" Ctx.emitError(CS.getInstruction(),
"inline asm error: This value"
" type register class is not natively supported!"); " type register class is not natively supported!");
report_fatal_error("inline asm error: This value type register " return;
"class is not natively supported!");
} }
} }
// Use the produced MatchedRegs object to // Use the produced MatchedRegs object to
@ -6241,7 +6241,7 @@ void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) {
Ctx.emitError(CS.getInstruction(), Ctx.emitError(CS.getInstruction(),
"invalid operand for inline asm constraint '" + "invalid operand for inline asm constraint '" +
Twine(OpInfo.ConstraintCode) + "'"); Twine(OpInfo.ConstraintCode) + "'");
break; return;
} }
// Add information to the INLINEASM node to know about this input. // Add information to the INLINEASM node to know about this input.
@ -6275,8 +6275,9 @@ void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) {
LLVMContext &Ctx = *DAG.getContext(); LLVMContext &Ctx = *DAG.getContext();
Ctx.emitError(CS.getInstruction(), Ctx.emitError(CS.getInstruction(),
"Don't know how to handle indirect register inputs yet " "Don't know how to handle indirect register inputs yet "
"for constraint '" + Twine(OpInfo.ConstraintCode) + "'"); "for constraint '" +
break; Twine(OpInfo.ConstraintCode) + "'");
return;
} }
// Copy the input into the appropriate registers. // Copy the input into the appropriate registers.
@ -6285,7 +6286,7 @@ void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) {
Ctx.emitError(CS.getInstruction(), Ctx.emitError(CS.getInstruction(),
"couldn't allocate input reg for constraint '" + "couldn't allocate input reg for constraint '" +
Twine(OpInfo.ConstraintCode) + "'"); Twine(OpInfo.ConstraintCode) + "'");
break; return;
} }
OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, getCurSDLoc(), OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, getCurSDLoc(),