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implement CodeGen/X86/inline-asm-x-scalar.ll:test3
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35802 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -2656,13 +2656,20 @@ void RegsForValue::getCopyToRegs(SDOperand Val, SelectionDAG &DAG,
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if (MVT::isVector(RegVT)) {
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if (MVT::isVector(RegVT)) {
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assert(Val.getValueType() == MVT::Vector &&"Not a vector-vector cast?");
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assert(Val.getValueType() == MVT::Vector &&"Not a vector-vector cast?");
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Val = DAG.getNode(ISD::VBIT_CONVERT, RegVT, Val);
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Val = DAG.getNode(ISD::VBIT_CONVERT, RegVT, Val);
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} else if (MVT::isInteger(RegVT)) {
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} else if (MVT::isInteger(RegVT) && MVT::isInteger(Val.getValueType())) {
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if (RegVT < ValueVT)
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if (RegVT < ValueVT)
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Val = DAG.getNode(ISD::TRUNCATE, RegVT, Val);
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Val = DAG.getNode(ISD::TRUNCATE, RegVT, Val);
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else
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else
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Val = DAG.getNode(ISD::ANY_EXTEND, RegVT, Val);
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Val = DAG.getNode(ISD::ANY_EXTEND, RegVT, Val);
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} else
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} else if (MVT::isFloatingPoint(RegVT) &&
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MVT::isFloatingPoint(Val.getValueType())) {
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Val = DAG.getNode(ISD::FP_EXTEND, RegVT, Val);
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Val = DAG.getNode(ISD::FP_EXTEND, RegVT, Val);
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} else if (MVT::getSizeInBits(RegVT) ==
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MVT::getSizeInBits(Val.getValueType())) {
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Val = DAG.getNode(ISD::BIT_CONVERT, RegVT, Val);
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} else {
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assert(0 && "Unknown mismatch!");
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}
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}
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}
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Chain = DAG.getCopyToReg(Chain, Regs[0], Val, Flag);
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Chain = DAG.getCopyToReg(Chain, Regs[0], Val, Flag);
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Flag = Chain.getValue(1);
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Flag = Chain.getValue(1);
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