diff --git a/include/llvm/Target/TargetLowering.h b/include/llvm/Target/TargetLowering.h
index 0ebf1d50549..9416afd25ec 100644
--- a/include/llvm/Target/TargetLowering.h
+++ b/include/llvm/Target/TargetLowering.h
@@ -372,13 +372,13 @@ public:
     return JumpBufAlignment;
   }
 
-  /// getLegalPreIndexedAddressBase - returns true by value, base pointer and
+  /// getPreIndexedAddressParts - returns true by value, base pointer and
   /// offset pointer and addressing mode by reference if the node's address
   /// can be legally represented as pre-indexed load / store address.
-  virtual bool getLegalPreIndexedAddressBase(SDNode *N, SDOperand &Base,
-                                             SDOperand &Offset,
-                                             ISD::MemOpAddrMode &AM,
-                                             SelectionDAG &DAG) {
+  virtual bool getPreIndexedAddressParts(SDNode *N, SDOperand &Base,
+                                         SDOperand &Offset,
+                                         ISD::MemOpAddrMode &AM,
+                                         SelectionDAG &DAG) {
     return false;
   }
   
diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index b85a6b7c128..74e92218e5b 100644
--- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -187,7 +187,7 @@ namespace {
         SDOperand BasePtr;
         SDOperand Offset;
         ISD::MemOpAddrMode AM = ISD::UNINDEXED;
-        if (TLI.getLegalPreIndexedAddressBase(N, BasePtr, Offset, AM, DAG)) {
+        if (TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG)) {
           // Try turning it into a pre-indexed load / store except when
           // 1) Another use of base ptr is a predecessor of N. If ptr is folded
           //    that would create a cycle.