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Make "mov" work for all Thumb2 MOV encodings
According to the ARM specification, "mov" is a valid mnemonic for all Thumb2 MOV encodings. To achieve this, the patch adds one instruction alias with a special range condition to avoid collision with the Thumb1 MOV. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188901 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -710,6 +710,11 @@ def imm0_65535_expr : Operand<i32> {
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let ParserMatchClass = Imm0_65535ExprAsmOperand;
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}
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def Imm256_65535ExprAsmOperand: ImmAsmOperand { let Name = "Imm256_65535Expr"; }
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def imm256_65535_expr : Operand<i32> {
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let ParserMatchClass = Imm256_65535ExprAsmOperand;
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}
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/// imm24b - True if the 32-bit immediate is encodable in 24 bits.
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def Imm24bitAsmOperand: ImmAsmOperand { let Name = "Imm24bit"; }
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def imm24b : Operand<i32>, ImmLeaf<i32, [{
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@ -1855,6 +1855,9 @@ def t2MOVi16 : T2I<(outs rGPR:$Rd), (ins imm0_65535_expr:$imm), IIC_iMOVi,
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let DecoderMethod = "DecodeT2MOVTWInstruction";
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}
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def : t2InstAlias<"mov${p} $Rd, $imm",
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(t2MOVi16 rGPR:$Rd, imm256_65535_expr:$imm, pred:$p)>;
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def t2MOVi16_ga_pcrel : PseudoInst<(outs rGPR:$Rd),
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(ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
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@ -867,6 +867,15 @@ public:
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int64_t Value = CE->getValue();
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return Value >= 0 && Value < 65536;
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}
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bool isImm256_65535Expr() const {
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if (!isImm()) return false;
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const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
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// If it's not a constant expression, it'll generate a fixup and be
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// handled later.
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if (!CE) return true;
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int64_t Value = CE->getValue();
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return Value >= 256 && Value < 65536;
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}
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bool isImm0_65535Expr() const {
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if (!isImm()) return false;
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const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
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@ -1323,8 +1323,15 @@ _func:
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movlo r1, #-1
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@ alias for mvn
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mov r3, #-3
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mov r3, #-3
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mov r11, #0xabcd
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movs r0, #1
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it ne
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movne r3, #15
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itt eq
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moveq r0, #255
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moveq r1, #256
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@ CHECK: movs r1, #21 @ encoding: [0x15,0x21]
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@ CHECK: movs.w r1, #21 @ encoding: [0x5f,0xf0,0x15,0x01]
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@ -1343,6 +1350,14 @@ _func:
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@ CHECK: it lo @ encoding: [0x38,0xbf]
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@ CHECK: movlo.w r1, #-1 @ encoding: [0x4f,0xf0,0xff,0x31]
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@ CHECK: mvn r3, #2 @ encoding: [0x6f,0xf0,0x02,0x03]
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@ CHECK: movw r11, #43981 @ encoding: [0x4a,0xf6,0xcd,0x3b]
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@ CHECK: movs r0, #1 @ encoding: [0x01,0x20]
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@ CHECK: it ne @ encoding: [0x18,0xbf]
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@ CHECK: movne r3, #15 @ encoding: [0x0f,0x23]
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@ CHECK: itt eq @ encoding: [0x04,0xbf]
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@ CHECK: moveq r0, #255 @ encoding: [0xff,0x20]
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@ CHECK: movweq r1, #256 @ encoding: [0x40,0xf2,0x00,0x11]
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@------------------------------------------------------------------------------
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@ MOV(shifted register)
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