6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-01-08 03:30:22 +00:00
Code Issues Projects Releases Wiki Activity

Fix 80-column and style

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139061 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bruno Cardoso Lopes 2011-09-03 00:46:40 +00:00
parent e4ccf8a86c
commit 1aab5515f6
1 changed files with 48 additions and 48 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

96
lib/Target/X86/X86InstrSSE.td
View File

@ -2415,13 +2415,13 @@ let Predicates = [HasAVX] in {
defm VMOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps, defm VMOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps,
"movmskps", SSEPackedSingle>, TB, VEX; "movmskps", SSEPackedSingle>, TB, VEX;
defm VMOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd, defm VMOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd,
"movmskpd", SSEPackedDouble>, TB, OpSize, "movmskpd", SSEPackedDouble>, TB,
VEX; OpSize, VEX;
defm VMOVMSKPSY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_ps_256, defm VMOVMSKPSY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_ps_256,
"movmskps", SSEPackedSingle>, TB, VEX; "movmskps", SSEPackedSingle>, TB, VEX;
defm VMOVMSKPDY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_pd_256, defm VMOVMSKPDY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_pd_256,
"movmskpd", SSEPackedDouble>, TB, OpSize, "movmskpd", SSEPackedDouble>, TB,
VEX; OpSize, VEX;
def : Pat<(i32 (X86fgetsign FR32:$src)), def : Pat<(i32 (X86fgetsign FR32:$src)),
(VMOVMSKPSrr32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src, (VMOVMSKPSrr32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src,
@ -2440,13 +2440,13 @@ let Predicates = [HasAVX] in {
def VMOVMSKPSr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src), def VMOVMSKPSr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
"movmskps\t{$src, $dst|$dst, $src}", [], SSEPackedSingle>, TB, VEX; "movmskps\t{$src, $dst|$dst, $src}", [], SSEPackedSingle>, TB, VEX;
def VMOVMSKPDr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src), def VMOVMSKPDr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
"movmskpd\t{$src, $dst|$dst, $src}", [], SSEPackedDouble>, TB, OpSize, "movmskpd\t{$src, $dst|$dst, $src}", [], SSEPackedDouble>, TB,
VEX; OpSize, VEX;
def VMOVMSKPSYr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src), def VMOVMSKPSYr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
"movmskps\t{$src, $dst|$dst, $src}", [], SSEPackedSingle>, TB, VEX; "movmskps\t{$src, $dst|$dst, $src}", [], SSEPackedSingle>, TB, VEX;
def VMOVMSKPDYr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src), def VMOVMSKPDYr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
"movmskpd\t{$src, $dst|$dst, $src}", [], SSEPackedDouble>, TB, OpSize, "movmskpd\t{$src, $dst|$dst, $src}", [], SSEPackedDouble>, TB,
VEX; OpSize, VEX;
} }
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
@ -2460,18 +2460,18 @@ let Predicates = [HasAVX] in {
let isReMaterializable = 1, isAsCheapAsAMove = 1, isCodeGenOnly = 1, let isReMaterializable = 1, isAsCheapAsAMove = 1, isCodeGenOnly = 1,
canFoldAsLoad = 1 in { canFoldAsLoad = 1 in {
// FIXME: Set encoding to pseudo! // FIXME: Set encoding to pseudo!
def FsFLD0SS : I<0xEF, MRMInitReg, (outs FR32:$dst), (ins), "", def FsFLD0SS : I<0xEF, MRMInitReg, (outs FR32:$dst), (ins), "",
[(set FR32:$dst, fp32imm0)]>, [(set FR32:$dst, fp32imm0)]>,
Requires<[HasSSE1]>, TB, OpSize; Requires<[HasSSE1]>, TB, OpSize;
def FsFLD0SD : I<0xEF, MRMInitReg, (outs FR64:$dst), (ins), "", def FsFLD0SD : I<0xEF, MRMInitReg, (outs FR64:$dst), (ins), "",
[(set FR64:$dst, fpimm0)]>, [(set FR64:$dst, fpimm0)]>,
Requires<[HasSSE2]>, TB, OpSize; Requires<[HasSSE2]>, TB, OpSize;
def VFsFLD0SS : I<0xEF, MRMInitReg, (outs FR32:$dst), (ins), "", def VFsFLD0SS : I<0xEF, MRMInitReg, (outs FR32:$dst), (ins), "",
[(set FR32:$dst, fp32imm0)]>, [(set FR32:$dst, fp32imm0)]>,
Requires<[HasAVX]>, TB, OpSize, VEX_4V; Requires<[HasAVX]>, TB, OpSize, VEX_4V;
def VFsFLD0SD : I<0xEF, MRMInitReg, (outs FR64:$dst), (ins), "", def VFsFLD0SD : I<0xEF, MRMInitReg, (outs FR64:$dst), (ins), "",
[(set FR64:$dst, fpimm0)]>, [(set FR64:$dst, fpimm0)]>,
Requires<[HasAVX]>, TB, OpSize, VEX_4V; Requires<[HasAVX]>, TB, OpSize, VEX_4V;
} }
// Alias instruction to do FR32 or FR64 reg-to-reg copy using movaps. Upper // Alias instruction to do FR32 or FR64 reg-to-reg copy using movaps. Upper
@ -2943,37 +2943,37 @@ def : Pat<(f32 (X86frcp (load addr:$src))),
Requires<[HasAVX, OptForSize]>; Requires<[HasAVX, OptForSize]>;
let Predicates = [HasAVX] in { let Predicates = [HasAVX] in {
def : Pat<(int_x86_sse_sqrt_ss VR128:$src), def : Pat<(int_x86_sse_sqrt_ss VR128:$src),
(INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)),
(VSQRTSSr (f32 (IMPLICIT_DEF)), (VSQRTSSr (f32 (IMPLICIT_DEF)),
(EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)), (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)),
sub_ss)>; sub_ss)>;
def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src), def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
(VSQRTSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>; (VSQRTSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
def : Pat<(int_x86_sse2_sqrt_sd VR128:$src), def : Pat<(int_x86_sse2_sqrt_sd VR128:$src),
(INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)),
(VSQRTSDr (f64 (IMPLICIT_DEF)), (VSQRTSDr (f64 (IMPLICIT_DEF)),
(EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd)), (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd)),
sub_sd)>; sub_sd)>;
def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src), def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
(VSQRTSDm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>; (VSQRTSDm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
def : Pat<(int_x86_sse_rsqrt_ss VR128:$src), def : Pat<(int_x86_sse_rsqrt_ss VR128:$src),
(INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)),
(VRSQRTSSr (f32 (IMPLICIT_DEF)), (VRSQRTSSr (f32 (IMPLICIT_DEF)),
(EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)), (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)),
sub_ss)>; sub_ss)>;
def : Pat<(int_x86_sse_rsqrt_ss sse_load_f32:$src), def : Pat<(int_x86_sse_rsqrt_ss sse_load_f32:$src),
(VRSQRTSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>; (VRSQRTSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
def : Pat<(int_x86_sse_rcp_ss VR128:$src), def : Pat<(int_x86_sse_rcp_ss VR128:$src),
(INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)),
(VRCPSSr (f32 (IMPLICIT_DEF)), (VRCPSSr (f32 (IMPLICIT_DEF)),
(EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)), (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)),
sub_ss)>; sub_ss)>;
def : Pat<(int_x86_sse_rcp_ss sse_load_f32:$src), def : Pat<(int_x86_sse_rcp_ss sse_load_f32:$src),
(VRCPSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>; (VRCPSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
} }
// Square root. // Square root.