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[ARM] In ARMAsmParser, MatchCoprocessorOperandName() permitted p10 and p11 as operands for coprocessor instructions, resulting in encodings that clash with FP/NEON instruction encodings

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194253 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Artyom Skrobov 2013-11-08 09:16:31 +00:00
parent 5f7259180c
commit 1b91231347
5 changed files with 34 additions and 28 deletions
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5
lib/Target/ARM/AsmParser/ARMAsmParser.cpp
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@ -2872,8 +2872,9 @@ static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) {
return -1;
switch (Name[2]) {
default: return -1;
case '0': return 10;
case '1': return 11;
// p10 and p11 are invalid for coproc instructions (reserved for FP/NEON)
case '0': return CoprocOp == 'p'? -1: 10;
case '1': return CoprocOp == 'p'? -1: 11;
case '2': return 12;
case '3': return 13;
case '4': return 14;

24
test/MC/ARM/basic-arm-instructions.s
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@ -460,11 +460,11 @@ Lforward:
@------------------------------------------------------------------------------
cdp p7, #1, c1, c1, c1, #4
cdp2 p7, #1, c1, c1, c1, #4
cdp2 p10, #0, c6, c12, c0, #7
cdp2 p12, #0, c6, c12, c0, #7
@ CHECK: cdp p7, #1, c1, c1, c1, #4 @ encoding: [0x81,0x17,0x11,0xee]
@ CHECK: cdp2 p7, #1, c1, c1, c1, #4 @ encoding: [0x81,0x17,0x11,0xfe]
@ CHECK: cdp2 p10, #0, c6, c12, c0, #7 @ encoding: [0xe0,0x6a,0x0c,0xfe]
@ CHECK: cdp2 p12, #0, c6, c12, c0, #7 @ encoding: [0xe0,0x6c,0x0c,0xfe]
cdpne p7, #1, c1, c1, c1, #4
@ CHECK: cdpne p7, #1, c1, c1, c1, #4 @ encoding: [0x81,0x17,0x11,0x1e]
@ -805,8 +805,8 @@ Lforward:
ldc2l p7, c1, [r8]
ldc2l p8, c0, [r9, #-224]
ldc2l p9, c1, [r10, #-120]!
ldc2l p10, c2, [r11], #16
ldc2l p11, c3, [r12], #-72
ldc2l p0, c2, [r11], #16
ldc2l p1, c3, [r12], #-72
ldc p12, c4, [r0, #4]
ldc p13, c5, [r1]
@ -846,8 +846,8 @@ Lforward:
@ CHECK: ldc2l p7, c1, [r8] @ encoding: [0x00,0x17,0xd8,0xfd]
@ CHECK: ldc2l p8, c0, [r9, #-224] @ encoding: [0x38,0x08,0x59,0xfd]
@ CHECK: ldc2l p9, c1, [r10, #-120]! @ encoding: [0x1e,0x19,0x7a,0xfd]
@ CHECK: ldc2l p10, c2, [r11], #16 @ encoding: [0x04,0x2a,0xfb,0xfc]
@ CHECK: ldc2l p11, c3, [r12], #-72 @ encoding: [0x12,0x3b,0x7c,0xfc]
@ CHECK: ldc2l p0, c2, [r11], #16 @ encoding: [0x04,0x20,0xfb,0xfc]
@ CHECK: ldc2l p1, c3, [r12], #-72 @ encoding: [0x12,0x31,0x7c,0xfc]
@ CHECK: ldc p12, c4, [r0, #4] @ encoding: [0x01,0x4c,0x90,0xed]
@ CHECK: ldc p13, c5, [r1] @ encoding: [0x00,0x5d,0x91,0xed]
@ -1078,12 +1078,12 @@ Lforward:
mrc p14, #0, r1, c1, c2, #4
mrc p15, #7, apsr_nzcv, c15, c6, #6
mrc2 p14, #0, r1, c1, c2, #4
mrc2 p10, #7, apsr_nzcv, c15, c0, #1
mrc2 p9, #7, apsr_nzcv, c15, c0, #1
@ CHECK: mrc p14, #0, r1, c1, c2, #4 @ encoding: [0x92,0x1e,0x11,0xee]
@ CHECK: mrc p15, #7, apsr_nzcv, c15, c6, #6 @ encoding: [0xd6,0xff,0xff,0xee]
@ CHECK: mrc2 p14, #0, r1, c1, c2, #4 @ encoding: [0x92,0x1e,0x11,0xfe]
@ CHECK: mrc2 p10, #7, apsr_nzcv, c15, c0, #1 @ encoding: [0x30,0xfa,0xff,0xfe]
@ CHECK: mrc2 p9, #7, apsr_nzcv, c15, c0, #1 @ encoding: [0x30,0xf9,0xff,0xfe]
mrceq p15, #7, apsr_nzcv, c15, c6, #6
@ CHECK: mrceq p15, #7, apsr_nzcv, c15, c6, #6 @ encoding: [0xd6,0xff,0xff,0x0e]
@ -2240,8 +2240,8 @@ Lforward:
stc2l p7, c1, [r8]
stc2l p8, c0, [r9, #-224]
stc2l p9, c1, [r10, #-120]!
stc2l p10, c2, [r11], #16
stc2l p11, c3, [r12], #-72
stc2l p0, c2, [r11], #16
stc2l p1, c3, [r12], #-72
stc p12, c4, [r0, #4]
stc p13, c5, [r1]
@ -2281,8 +2281,8 @@ Lforward:
@ CHECK: stc2l p7, c1, [r8] @ encoding: [0x00,0x17,0xc8,0xfd]
@ CHECK: stc2l p8, c0, [r9, #-224] @ encoding: [0x38,0x08,0x49,0xfd]
@ CHECK: stc2l p9, c1, [r10, #-120]! @ encoding: [0x1e,0x19,0x6a,0xfd]
@ CHECK: stc2l p10, c2, [r11], #16 @ encoding: [0x04,0x2a,0xeb,0xfc]
@ CHECK: stc2l p11, c3, [r12], #-72 @ encoding: [0x12,0x3b,0x6c,0xfc]
@ CHECK: stc2l p0, c2, [r11], #16 @ encoding: [0x04,0x20,0xeb,0xfc]
@ CHECK: stc2l p1, c3, [r12], #-72 @ encoding: [0x12,0x31,0x6c,0xfc]
@ CHECK: stc p12, c4, [r0, #4] @ encoding: [0x01,0x4c,0x80,0xed]
@ CHECK: stc p13, c5, [r1] @ encoding: [0x00,0x5d,0x81,0xed]

24
test/MC/ARM/basic-thumb2-instructions.s
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@ -662,8 +662,8 @@ _func:
ldc2l p7, c1, [r8]
ldc2l p8, c0, [r9, #-224]
ldc2l p9, c1, [r10, #-120]!
ldc2l p10, c2, [r11], #16
ldc2l p11, c3, [r12], #-72
ldc2l p0, c2, [r11], #16
ldc2l p1, c3, [r12], #-72
ldc p12, c4, [r0, #4]
ldc p13, c5, [r1]
@ -690,8 +690,8 @@ _func:
@ CHECK: ldc2l p7, c1, [r8] @ encoding: [0xd8,0xfd,0x00,0x17]
@ CHECK: ldc2l p8, c0, [r9, #-224] @ encoding: [0x59,0xfd,0x38,0x08]
@ CHECK: ldc2l p9, c1, [r10, #-120]! @ encoding: [0x7a,0xfd,0x1e,0x19]
@ CHECK: ldc2l p10, c2, [r11], #16 @ encoding: [0xfb,0xfc,0x04,0x2a]
@ CHECK: ldc2l p11, c3, [r12], #-72 @ encoding: [0x7c,0xfc,0x12,0x3b]
@ CHECK: ldc2l p0, c2, [r11], #16 @ encoding: [0xfb,0xfc,0x04,0x20]
@ CHECK: ldc2l p1, c3, [r12], #-72 @ encoding: [0x7c,0xfc,0x12,0x31]
@ CHECK: ldc p12, c4, [r0, #4] @ encoding: [0x90,0xed,0x01,0x4c]
@ CHECK: ldc p13, c5, [r1] @ encoding: [0x91,0xed,0x00,0x5d]
@ -1417,17 +1417,17 @@ _func:
@------------------------------------------------------------------------------
mrc p14, #0, r1, c1, c2, #4
mrc p15, #7, apsr_nzcv, c15, c6, #6
mrc p11, #1, r1, c2, c2
mrc p9, #1, r1, c2, c2
mrc2 p12, #3, r3, c3, c4
mrc2 p14, #0, r1, c1, c2, #4
mrc2 p10, #7, apsr_nzcv, c15, c0, #1
mrc2 p8, #7, apsr_nzcv, c15, c0, #1
@ CHECK: mrc p14, #0, r1, c1, c2, #4 @ encoding: [0x11,0xee,0x92,0x1e]
@ CHECK: mrc p15, #7, apsr_nzcv, c15, c6, #6 @ encoding: [0xff,0xee,0xd6,0xff]
@ CHECK: mrc p11, #1, r1, c2, c2, #0 @ encoding: [0x32,0xee,0x12,0x1b]
@ CHECK: mrc p9, #1, r1, c2, c2, #0 @ encoding: [0x32,0xee,0x12,0x19]
@ CHECK: mrc2 p12, #3, r3, c3, c4, #0 @ encoding: [0x73,0xfe,0x14,0x3c]
@ CHECK: mrc2 p14, #0, r1, c1, c2, #4 @ encoding: [0x11,0xfe,0x92,0x1e]
@ CHECK: mrc2 p10, #7, apsr_nzcv, c15, c0, #1 @ encoding: [0xff,0xfe,0x30,0xfa]
@ CHECK: mrc2 p8, #7, apsr_nzcv, c15, c0, #1 @ encoding: [0xff,0xfe,0x30,0xf8]
@------------------------------------------------------------------------------
@ MRRC/MRRC2
@ -2554,8 +2554,8 @@ _func:
stc2l p7, c1, [r8]
stc2l p8, c0, [r9, #-224]
stc2l p9, c1, [r10, #-120]!
stc2l p10, c2, [r11], #16
stc2l p11, c3, [r12], #-72
stc2l p0, c2, [r11], #16
stc2l p1, c3, [r12], #-72
stc p12, c4, [r0, #4]
stc p13, c5, [r1]
@ -2582,8 +2582,8 @@ _func:
@ CHECK: stc2l p7, c1, [r8] @ encoding: [0xc8,0xfd,0x00,0x17]
@ CHECK: stc2l p8, c0, [r9, #-224] @ encoding: [0x49,0xfd,0x38,0x08]
@ CHECK: stc2l p9, c1, [r10, #-120]! @ encoding: [0x6a,0xfd,0x1e,0x19]
@ CHECK: stc2l p10, c2, [r11], #16 @ encoding: [0xeb,0xfc,0x04,0x2a]
@ CHECK: stc2l p11, c3, [r12], #-72 @ encoding: [0x6c,0xfc,0x12,0x3b]
@ CHECK: stc2l p0, c2, [r11], #16 @ encoding: [0xeb,0xfc,0x04,0x20]
@ CHECK: stc2l p1, c3, [r12], #-72 @ encoding: [0x6c,0xfc,0x12,0x31]
@ CHECK: stc p12, c4, [r0, #4] @ encoding: [0x80,0xed,0x01,0x4c]
@ CHECK: stc p13, c5, [r1] @ encoding: [0x81,0xed,0x00,0x5d]

5
test/MC/ARM/diagnostics.s
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@ -151,6 +151,11 @@
@ CHECK-ERRORS: error: immediate operand must be in the range [0,15]
@ CHECK-ERRORS: error: immediate operand must be in the range [0,15]
@ p10 and p11 are reserved for NEON
mcr p10, #2, r5, c1, c1, #4
mcrr p11, #8, r5, r4, c1
@ CHECK-ERRORS: error: invalid operand for instruction
@ CHECK-ERRORS: error: invalid operand for instruction
@ Out of range immediate for MOV
movw r9, 0x10000

4
test/MC/ARM/thumb-only-conditionals.s
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@ -40,10 +40,10 @@
@ CHECK-NEXT: mcrr2gt p7, #15, r5, r4, c1
ite eq
mrceq p11, #1, r1, c2, c2
mrceq p9, #1, r1, c2, c2
mrc2ne p12, #3, r3, c3, c4
@ CHECK: ite eq
@ CHECK-NEXT: mrceq p11, #1, r1, c2, c2
@ CHECK-NEXT: mrceq p9, #1, r1, c2, c2
@ CHECK-NEXT: mrc2ne p12, #3, r3, c3, c4
itt lo