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Rename M_PREDICATED to M_PREDICABLE; Move TargetInstrInfo::isPredicatable() to MachineInstr::isPredicable().

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37115 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
2007-05-16 20:43:42 +00:00
parent 6551dcdd8a
commit 1bccb49082
2 changed files with 10 additions and 15 deletions
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4
include/llvm/CodeGen/MachineInstr.h
View File

@@ -394,6 +394,10 @@ public:
return true;
}
/// isPredicable - True if the instruction can be converted into a
/// predicated instruction.
bool isPredicable() const;
/// clone - Create a copy of 'this' instruction that is identical in
/// all ways except the the instruction has no parent, prev, or next.
MachineInstr* clone() const { return new MachineInstr(*this); }

21
include/llvm/Target/TargetInstrInfo.h
View File

@@ -74,9 +74,9 @@ const unsigned M_USES_CUSTOM_DAG_SCHED_INSERTION = 1 << 10;
// operands in addition to the minimum number operands specified.
const unsigned M_VARIABLE_OPS = 1 << 11;
// M_PREDICATED - Set if this instruction has a predicate that controls its
// execution.
const unsigned M_PREDICATED = 1 << 12;
// M_PREDICABLE - Set if this instruction has a predicate operand that
// controls execution. It may be set to 'always'.
const unsigned M_PREDICABLE = 1 << 12;
// M_REMATERIALIZIBLE - Set if this instruction can be trivally re-materialized
// at any time, e.g. constant generation, load from constant pool.
@@ -208,8 +208,8 @@ public:
return get(Opcode).Flags & M_RET_FLAG;
}
bool isPredicated(MachineOpCode Opcode) const {
return get(Opcode).Flags & M_PREDICATED;
bool isPredicable(MachineOpCode Opcode) const {
return get(Opcode).Flags & M_PREDICABLE;
}
bool isReMaterializable(MachineOpCode Opcode) const {
return get(Opcode).Flags & M_REMATERIALIZIBLE;
@@ -389,19 +389,10 @@ public:
abort();
}
/// isPredicatable - True if the instruction can be converted into a
/// predicated instruction.
virtual bool isPredicatable(MachineInstr *MI) const {
return false;
}
/// PredicateInstruction - Convert the instruction into a predicated
/// instruction.
virtual void PredicateInstruction(MachineInstr *MI,
std::vector<MachineOperand> &Cond) const {
assert(0 && "Target didn't implement PredicateInstruction!");
abort();
}
std::vector<MachineOperand> &Cond) const;
/// getPointerRegClass - Returns a TargetRegisterClass used for pointer
/// values.