Return 0 instead of false.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168076 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakub Staszak
2012-11-15 19:40:29 +00:00
parent f38aa4272c
commit 1c1c49372c

View File

@ -2154,13 +2154,13 @@ unsigned X86FastISel::TargetMaterializeAlloca(const AllocaInst *C) {
unsigned X86FastISel::TargetMaterializeFloatZero(const ConstantFP *CF) { unsigned X86FastISel::TargetMaterializeFloatZero(const ConstantFP *CF) {
MVT VT; MVT VT;
if (!isTypeLegal(CF->getType(), VT)) if (!isTypeLegal(CF->getType(), VT))
return false; return 0;
// Get opcode and regclass for the given zero. // Get opcode and regclass for the given zero.
unsigned Opc = 0; unsigned Opc = 0;
const TargetRegisterClass *RC = NULL; const TargetRegisterClass *RC = NULL;
switch (VT.SimpleTy) { switch (VT.SimpleTy) {
default: return false; default: return 0;
case MVT::f32: case MVT::f32:
if (X86ScalarSSEf32) { if (X86ScalarSSEf32) {
Opc = X86::FsFLD0SS; Opc = X86::FsFLD0SS;
@ -2181,7 +2181,7 @@ unsigned X86FastISel::TargetMaterializeFloatZero(const ConstantFP *CF) {
break; break;
case MVT::f80: case MVT::f80:
// No f80 support yet. // No f80 support yet.
return false; return 0;
} }
unsigned ResultReg = createResultReg(RC); unsigned ResultReg = createResultReg(RC);