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Determine allocation 'preference' with right register class. I haven't seen this changing codegen so no test case.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70351 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2009-04-29 00:42:27 +00:00
parent 5e5cb7985d
commit 1c2f6da331
1 changed files with 10 additions and 8 deletions
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18
lib/CodeGen/RegAllocLinearScan.cpp
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@ -799,8 +799,14 @@ void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur)
Reg = SrcReg; Reg = SrcReg;
else if (vrm_->isAssignedReg(SrcReg)) else if (vrm_->isAssignedReg(SrcReg))
Reg = vrm_->getPhys(SrcReg); Reg = vrm_->getPhys(SrcReg);
if (Reg && allocatableRegs_[Reg] && RC->contains(Reg)) if (Reg) {
cur->preference = Reg; if (SrcSubReg)
Reg = tri_->getSubReg(Reg, SrcSubReg);
if (DstSubReg)
Reg = tri_->getMatchingSuperReg(Reg, DstSubReg, RC);
if (Reg && allocatableRegs_[Reg] && RC->contains(Reg))
cur->preference = Reg;
}
} }
} }
} }
@ -1265,14 +1271,10 @@ unsigned RALinScan::getFreePhysReg(LiveInterval *cur) {
// If copy coalescer has assigned a "preferred" register, check if it's // If copy coalescer has assigned a "preferred" register, check if it's
// available first. // available first.
if (cur->preference) { if (cur->preference) {
DOUT << "(preferred: " << tri_->getName(cur->preference) << ") ";
if (prt_->isRegAvail(cur->preference) && if (prt_->isRegAvail(cur->preference) &&
RC->contains(cur->preference)) { RC->contains(cur->preference))
DOUT << "\t\tassigned the preferred register: "
<< tri_->getName(cur->preference) << "\n";
return cur->preference; return cur->preference;
} else
DOUT << "\t\tunable to assign the preferred register: "
<< tri_->getName(cur->preference) << "\n";
} }
if (!DowngradedRegs.empty()) { if (!DowngradedRegs.empty()) {