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Loop Vectorizer minor changes in the code -

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some comments, function names, identation.

Reviewed here: http://reviews.llvm.org/D6527


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224218 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Elena Demikhovsky 2014-12-14 09:43:50 +00:00
parent a53d2268a9
commit 1c3a1516f8
4 changed files with 14 additions and 14 deletions
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4
include/llvm/Analysis/TargetTransformInfo.h
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@ -274,8 +274,8 @@ public:
/// AVX2 allows masks for consecutive load and store for i32 and i64 elements.
/// AVX-512 architecture will also allow masks for non-consecutive memory
/// accesses.
virtual bool isLegalPredicatedStore(Type *DataType, int Consecutive) const;
virtual bool isLegalPredicatedLoad (Type *DataType, int Consecutive) const;
virtual bool isLegalMaskedStore(Type *DataType, int Consecutive) const;
virtual bool isLegalMaskedLoad (Type *DataType, int Consecutive) const;
/// \brief Return the cost of the scaling factor used in the addressing
/// mode represented by AM for this target, for a load/store

8
lib/Analysis/TargetTransformInfo.cpp
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@ -101,13 +101,13 @@ bool TargetTransformInfo::isLegalICmpImmediate(int64_t Imm) const {
return PrevTTI->isLegalICmpImmediate(Imm);
}
bool TargetTransformInfo::isLegalPredicatedLoad(Type *DataType,
int Consecutive) const {
bool TargetTransformInfo::isLegalMaskedLoad(Type *DataType,
int Consecutive) const {
return false;
}
bool TargetTransformInfo::isLegalPredicatedStore(Type *DataType,
int Consecutive) const {
bool TargetTransformInfo::isLegalMaskedStore(Type *DataType,
int Consecutive) const {
return false;
}

10
lib/Target/X86/X86TargetTransformInfo.cpp
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@ -111,8 +111,8 @@ public:
Type *Ty) const override;
unsigned getIntImmCost(Intrinsic::ID IID, unsigned Idx, const APInt &Imm,
Type *Ty) const override;
bool isLegalPredicatedLoad (Type *DataType, int Consecutive) const override;
bool isLegalPredicatedStore(Type *DataType, int Consecutive) const override;
bool isLegalMaskedLoad (Type *DataType, int Consecutive) const override;
bool isLegalMaskedStore(Type *DataType, int Consecutive) const override;
/// @}
};
@ -1159,7 +1159,7 @@ unsigned X86TTI::getIntImmCost(Intrinsic::ID IID, unsigned Idx,
return X86TTI::getIntImmCost(Imm, Ty);
}
bool X86TTI::isLegalPredicatedLoad(Type *DataType, int Consecutive) const {
bool X86TTI::isLegalMaskedLoad(Type *DataType, int Consecutive) const {
int ScalarWidth = DataType->getScalarSizeInBits();
// Todo: AVX512 allows gather/scatter, works with strided and random as well
@ -1170,7 +1170,7 @@ bool X86TTI::isLegalPredicatedLoad(Type *DataType, int Consecutive) const {
return false;
}
bool X86TTI::isLegalPredicatedStore(Type *DataType, int Consecutive) const {
return isLegalPredicatedLoad(DataType, Consecutive);
bool X86TTI::isLegalMaskedStore(Type *DataType, int Consecutive) const {
return isLegalMaskedLoad(DataType, Consecutive);
}

6
lib/Transforms/Vectorize/LoopVectorize.cpp
View File

@ -1871,7 +1871,7 @@ void InnerLoopVectorizer::vectorizeMemoryInstruction(Instruction *Instr) {
if (Reverse) {
// If the address is consecutive but reversed, then the
// wide store needs to start at the last vector element.
// wide load needs to start at the last vector element.
PartPtr = Builder.CreateGEP(Ptr, Builder.getInt32(-Part * VF));
PartPtr = Builder.CreateGEP(PartPtr, Builder.getInt32(1 - VF));
}
@ -5341,7 +5341,7 @@ bool LoopVectorizationLegality::blockCanBePredicated(BasicBlock *BB,
case Instruction::SDiv:
case Instruction::URem:
case Instruction::SRem:
return false;
return false;
}
}
@ -5385,7 +5385,7 @@ LoopVectorizationCostModel::selectVectorizationFactor(bool OptForSize) {
MaxVectorSize = 1;
}
assert(MaxVectorSize <= 32 && "Did not expect to pack so many elements"
assert(MaxVectorSize <= 64 && "Did not expect to pack so many elements"
" into one vector!");
unsigned VF = MaxVectorSize;