6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-01-07 11:33:44 +00:00
Code Issues Projects Releases Wiki Activity

Added the x86 INT instructions; both the special-case INT 3 and the general-case

Browse Source 
INT i8.  These instructions are only for interpretation by disassemblers, not
for emission, so they do not as yet have patterns.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78630 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Sean Callanan 2009-08-11 01:09:06 +00:00
parent f35290ce8d
commit 1c5cf1b378
1 changed files with 4 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
lib/Target/X86/X86InstrInfo.td
View File

@ -518,6 +518,10 @@ let neverHasSideEffects = 1 in {
"nopl\t$zero", []>, TB;
}
// Trap
def INT3 : I<0xcc, RawFrm, (outs), (ins), "int 3", []>;
def INT : I<0xcd, RawFrm, (outs), (ins i8imm:$trap), "int\t$trap", []>;
// PIC base
let neverHasSideEffects = 1, isNotDuplicable = 1, Uses = [ESP] in
def MOVPC32r : Ii32<0xE8, Pseudo, (outs GR32:$reg), (ins piclabel:$label),