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ARM target should allow codegenprep to duplicate ret instructions to enable tailcall opt. rdar://11140249

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153717 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2012-03-30 01:24:39 +00:00
parent c459d31164
commit 1c80f56268
2 changed files with 43 additions and 1 deletions
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2
lib/Target/ARM/ARMISelLowering.cpp
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@ -1990,7 +1990,7 @@ bool ARMTargetLowering::isUsedByReturnOnly(SDNode *N) const {
}
bool ARMTargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
if (!EnableARMTailCalls)
if (!EnableARMTailCalls && !Subtarget->supportsTailCall())
return false;
if (!CI->isTailCall())

42
test/CodeGen/ARM/call-tc.ll
View File

@ -96,3 +96,45 @@ bb:
tail call void @foo() nounwind
ret void
}
; Make sure codegenprep is duplicating ret instructions to enable tail calls.
; rdar://11140249
define i32 @t8(i32 %x) nounwind ssp {
entry:
; CHECKT2D: t8:
; CHECKT2D-NOT: push
; CHECKT2D-NOT
%and = and i32 %x, 1
%tobool = icmp eq i32 %and, 0
br i1 %tobool, label %if.end, label %if.then
if.then: ; preds = %entry
; CHECKT2D: bne.w _a
%call = tail call i32 @a(i32 %x) nounwind
br label %return
if.end: ; preds = %entry
%and1 = and i32 %x, 2
%tobool2 = icmp eq i32 %and1, 0
br i1 %tobool2, label %if.end5, label %if.then3
if.then3: ; preds = %if.end
; CHECKT2D: bne.w _b
%call4 = tail call i32 @b(i32 %x) nounwind
br label %return
if.end5: ; preds = %if.end
; CHECKT2D: b.w _c
%call6 = tail call i32 @c(i32 %x) nounwind
br label %return
return: ; preds = %if.end5, %if.then3, %if.then
%retval.0 = phi i32 [ %call, %if.then ], [ %call4, %if.then3 ], [ %call6, %if.end5 ]
ret i32 %retval.0
}
declare i32 @a(i32)
declare i32 @b(i32)
declare i32 @c(i32)