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[mips][msa] Fix vector insertions where the index is variable
Summary: This isn't supported directly so we rotate the vector by the desired number of elements, insert to element zero, then rotate back. The i64 case generates rather poor code on MIPS32. There is an obvious optimisation to be made in future (do both insert.w's inside a shared rotate/unrotate sequence) but for now it's sufficient to select valid code instead of aborting. Depends on D3536 Reviewers: matheusalmeida Reviewed By: matheusalmeida Differential Revision: http://reviews.llvm.org/D3537 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207640 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Daniel Sanders
parent
4e29e3a10a
commit
1c8add9978
@ -1505,6 +1505,15 @@ class MSA_INSERT_PSEUDO_BASE<SDPatternOperator OpNode, ValueType Ty,
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string Constraints = "$wd = $wd_in";
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}
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class MSA_INSERT_VIDX_PSEUDO_BASE<SDPatternOperator OpNode, ValueType Ty,
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RegisterOperand ROWD, RegisterOperand ROFS> :
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MSAPseudo<(outs ROWD:$wd), (ins ROWD:$wd_in, GPR32Opnd:$n, ROFS:$fs),
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[(set ROWD:$wd, (OpNode (Ty ROWD:$wd_in), ROFS:$fs,
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GPR32Opnd:$n))]> {
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bit usesCustomInserter = 1;
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string Constraints = "$wd = $wd_in";
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}
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class MSA_INSVE_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
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RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
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InstrItinClass itin = NoItinerary> {
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@ -2300,11 +2309,25 @@ class INSERT_W_DESC : MSA_INSERT_DESC_BASE<"insert.w", vinsert_v4i32,
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class INSERT_D_DESC : MSA_INSERT_DESC_BASE<"insert.d", vinsert_v2i64,
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MSA128DOpnd, GPR64Opnd>;
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class INSERT_B_VIDX_PSEUDO_DESC :
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MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v16i8, MSA128BOpnd, GPR32Opnd>;
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class INSERT_H_VIDX_PSEUDO_DESC :
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MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v8i16, MSA128HOpnd, GPR32Opnd>;
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class INSERT_W_VIDX_PSEUDO_DESC :
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MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v4i32, MSA128WOpnd, GPR32Opnd>;
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class INSERT_D_VIDX_PSEUDO_DESC :
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MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v2i64, MSA128DOpnd, GPR64Opnd>;
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class INSERT_FW_PSEUDO_DESC : MSA_INSERT_PSEUDO_BASE<vector_insert, v4f32,
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MSA128WOpnd, FGR32Opnd>;
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class INSERT_FD_PSEUDO_DESC : MSA_INSERT_PSEUDO_BASE<vector_insert, v2f64,
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MSA128DOpnd, FGR64Opnd>;
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class INSERT_FW_VIDX_PSEUDO_DESC :
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MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v4f32, MSA128WOpnd, FGR32Opnd>;
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class INSERT_FD_VIDX_PSEUDO_DESC :
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MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v2f64, MSA128DOpnd, FGR64Opnd>;
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class INSVE_B_DESC : MSA_INSVE_DESC_BASE<"insve.b", insve_v16i8,
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MSA128BOpnd>;
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class INSVE_H_DESC : MSA_INSVE_DESC_BASE<"insve.h", insve_v8i16,
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@ -3214,6 +3237,13 @@ let DecoderMethod = "DecodeINSVE_DF" in {
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def INSERT_FW_PSEUDO : INSERT_FW_PSEUDO_DESC;
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def INSERT_FD_PSEUDO : INSERT_FD_PSEUDO_DESC;
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def INSERT_B_VIDX_PSEUDO : INSERT_B_VIDX_PSEUDO_DESC;
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def INSERT_H_VIDX_PSEUDO : INSERT_H_VIDX_PSEUDO_DESC;
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def INSERT_W_VIDX_PSEUDO : INSERT_W_VIDX_PSEUDO_DESC;
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def INSERT_D_VIDX_PSEUDO : INSERT_D_VIDX_PSEUDO_DESC;
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def INSERT_FW_VIDX_PSEUDO : INSERT_FW_VIDX_PSEUDO_DESC;
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def INSERT_FD_VIDX_PSEUDO : INSERT_FD_VIDX_PSEUDO_DESC;
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def LD_B: LD_B_ENC, LD_B_DESC;
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def LD_H: LD_H_ENC, LD_H_DESC;
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def LD_W: LD_W_ENC, LD_W_DESC;
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@ -1054,6 +1054,18 @@ MipsSETargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
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return emitINSERT_FW(MI, BB);
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case Mips::INSERT_FD_PSEUDO:
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return emitINSERT_FD(MI, BB);
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case Mips::INSERT_B_VIDX_PSEUDO:
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return emitINSERT_DF_VIDX(MI, BB, 1, false);
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case Mips::INSERT_H_VIDX_PSEUDO:
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return emitINSERT_DF_VIDX(MI, BB, 2, false);
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case Mips::INSERT_W_VIDX_PSEUDO:
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return emitINSERT_DF_VIDX(MI, BB, 4, false);
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case Mips::INSERT_D_VIDX_PSEUDO:
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return emitINSERT_DF_VIDX(MI, BB, 8, false);
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case Mips::INSERT_FW_VIDX_PSEUDO:
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return emitINSERT_DF_VIDX(MI, BB, 4, true);
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case Mips::INSERT_FD_VIDX_PSEUDO:
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return emitINSERT_DF_VIDX(MI, BB, 8, true);
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case Mips::FILL_FW_PSEUDO:
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return emitFILL_FW(MI, BB);
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case Mips::FILL_FD_PSEUDO:
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@ -2887,6 +2899,131 @@ MipsSETargetLowering::emitINSERT_FD(MachineInstr *MI,
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return BB;
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}
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// Emit the INSERT_([BHWD]|F[WD])_VIDX pseudo instruction.
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//
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// For integer:
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// (INSERT_([BHWD]|F[WD])_PSEUDO $wd, $wd_in, $n, $rs)
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// =>
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// (SLL $lanetmp1, $lane, <log2size)
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// (SLD_B $wdtmp1, $wd_in, $wd_in, $lanetmp1)
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// (INSERT_[BHWD], $wdtmp2, $wdtmp1, 0, $rs)
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// (NEG $lanetmp2, $lanetmp1)
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// (SLD_B $wd, $wdtmp2, $wdtmp2, $lanetmp2)
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//
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// For floating point:
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// (INSERT_([BHWD]|F[WD])_PSEUDO $wd, $wd_in, $n, $fs)
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// =>
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// (SUBREG_TO_REG $wt, $fs, <subreg>)
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// (SLL $lanetmp1, $lane, <log2size)
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// (SLD_B $wdtmp1, $wd_in, $wd_in, $lanetmp1)
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// (INSVE_[WD], $wdtmp2, 0, $wdtmp1, 0)
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// (NEG $lanetmp2, $lanetmp1)
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// (SLD_B $wd, $wdtmp2, $wdtmp2, $lanetmp2)
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MachineBasicBlock *
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MipsSETargetLowering::emitINSERT_DF_VIDX(MachineInstr *MI,
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MachineBasicBlock *BB,
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unsigned EltSizeInBytes,
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bool IsFP) const {
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const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
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MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
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DebugLoc DL = MI->getDebugLoc();
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unsigned Wd = MI->getOperand(0).getReg();
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unsigned SrcVecReg = MI->getOperand(1).getReg();
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unsigned LaneReg = MI->getOperand(2).getReg();
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unsigned SrcValReg = MI->getOperand(3).getReg();
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const TargetRegisterClass *VecRC = nullptr;
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const TargetRegisterClass *GPRRC = isGP64bit() ? &Mips::GPR64RegClass
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: &Mips::GPR32RegClass;
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unsigned EltLog2Size;
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unsigned InsertOp = 0;
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unsigned InsveOp = 0;
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switch (EltSizeInBytes) {
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default:
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llvm_unreachable("Unexpected size");
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case 1:
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EltLog2Size = 0;
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InsertOp = Mips::INSERT_B;
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InsveOp = Mips::INSVE_B;
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VecRC = &Mips::MSA128BRegClass;
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break;
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case 2:
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EltLog2Size = 1;
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InsertOp = Mips::INSERT_H;
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InsveOp = Mips::INSVE_H;
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VecRC = &Mips::MSA128HRegClass;
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break;
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case 4:
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EltLog2Size = 2;
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InsertOp = Mips::INSERT_W;
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InsveOp = Mips::INSVE_W;
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VecRC = &Mips::MSA128WRegClass;
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break;
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case 8:
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EltLog2Size = 3;
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InsertOp = Mips::INSERT_D;
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InsveOp = Mips::INSVE_D;
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VecRC = &Mips::MSA128DRegClass;
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break;
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}
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if (IsFP) {
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unsigned Wt = RegInfo.createVirtualRegister(VecRC);
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BuildMI(*BB, MI, DL, TII->get(Mips::SUBREG_TO_REG), Wt)
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.addImm(0)
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.addReg(SrcValReg)
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.addImm(EltSizeInBytes == 8 ? Mips::sub_64 : Mips::sub_lo);
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SrcValReg = Wt;
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}
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// Convert the lane index into a byte index
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if (EltSizeInBytes != 1) {
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unsigned LaneTmp1 = RegInfo.createVirtualRegister(GPRRC);
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BuildMI(*BB, MI, DL, TII->get(Mips::SLL), LaneTmp1)
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.addReg(LaneReg)
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.addImm(EltLog2Size);
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LaneReg = LaneTmp1;
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}
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// Rotate bytes around so that the desired lane is element zero
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unsigned WdTmp1 = RegInfo.createVirtualRegister(VecRC);
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BuildMI(*BB, MI, DL, TII->get(Mips::SLD_B), WdTmp1)
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.addReg(SrcVecReg)
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.addReg(SrcVecReg)
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.addReg(LaneReg);
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unsigned WdTmp2 = RegInfo.createVirtualRegister(VecRC);
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if (IsFP) {
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// Use insve.df to insert to element zero
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BuildMI(*BB, MI, DL, TII->get(InsveOp), WdTmp2)
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.addReg(WdTmp1)
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.addImm(0)
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.addReg(SrcValReg)
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.addImm(0);
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} else {
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// Use insert.df to insert to element zero
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BuildMI(*BB, MI, DL, TII->get(InsertOp), WdTmp2)
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.addReg(WdTmp1)
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.addReg(SrcValReg)
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.addImm(0);
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}
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// Rotate elements the rest of the way for a full rotation.
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// sld.df inteprets $rt modulo the number of columns so we only need to negate
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// the lane index to do this.
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unsigned LaneTmp2 = RegInfo.createVirtualRegister(GPRRC);
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BuildMI(*BB, MI, DL, TII->get(Mips::SUB), LaneTmp2)
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.addReg(Mips::ZERO)
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.addReg(LaneReg);
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BuildMI(*BB, MI, DL, TII->get(Mips::SLD_B), Wd)
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.addReg(WdTmp2)
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.addReg(WdTmp2)
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.addReg(LaneTmp2);
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MI->eraseFromParent(); // The pseudo instruction is gone now.
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return BB;
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}
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// Emit the FILL_FW pseudo instruction.
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//
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// fill_fw_pseudo $wd, $fs
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@ -98,6 +98,11 @@ namespace llvm {
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/// \brief Emit the INSERT_FD pseudo instruction
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MachineBasicBlock *emitINSERT_FD(MachineInstr *MI,
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MachineBasicBlock *BB) const;
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/// \brief Emit the INSERT_([BHWD]|F[WD])_VIDX pseudo instruction
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MachineBasicBlock *emitINSERT_DF_VIDX(MachineInstr *MI,
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MachineBasicBlock *BB,
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unsigned EltSizeInBytes,
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bool IsFP) const;
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/// \brief Emit the FILL_FW pseudo instruction
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MachineBasicBlock *emitFILL_FW(MachineInstr *MI,
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MachineBasicBlock *BB) const;
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@ -673,6 +673,129 @@ define void @insert_v2i64(i64 %a) nounwind {
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; MIPS32-AE: .size insert_v2i64
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}
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define void @insert_v16i8_vidx(i32 %a) nounwind {
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; MIPS32-AE: insert_v16i8_vidx:
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%1 = load <16 x i8>* @v16i8
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; MIPS32-AE-DAG: ld.b [[R1:\$w[0-9]+]],
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%2 = load i32* @i32
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; MIPS32-AE-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)(
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; MIPS32-AE-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]])
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%a2 = trunc i32 %a to i8
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%a3 = sext i8 %a2 to i32
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%a4 = trunc i32 %a3 to i8
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; MIPS32-AE-NOT: andi
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; MIPS32-AE-NOT: sra
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%3 = insertelement <16 x i8> %1, i8 %a4, i32 %2
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; MIPS32-AE-DAG: sld.b [[R1]], [[R1]]{{\[}}[[IDX]]]
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; MIPS32-AE-DAG: insert.b [[R1]][0], $4
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; MIPS32-AE-DAG: neg [[NIDX:\$[0-9]+]], [[IDX]]
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; MIPS32-AE-DAG: sld.b [[R1]], [[R1]]{{\[}}[[NIDX]]]
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store <16 x i8> %3, <16 x i8>* @v16i8
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; MIPS32-AE-DAG: st.b [[R1]]
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ret void
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; MIPS32-AE: .size insert_v16i8_vidx
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}
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define void @insert_v8i16_vidx(i32 %a) nounwind {
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; MIPS32-AE: insert_v8i16_vidx:
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%1 = load <8 x i16>* @v8i16
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; MIPS32-AE-DAG: ld.h [[R1:\$w[0-9]+]],
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%2 = load i32* @i32
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; MIPS32-AE-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)(
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; MIPS32-AE-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]])
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%a2 = trunc i32 %a to i16
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%a3 = sext i16 %a2 to i32
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%a4 = trunc i32 %a3 to i16
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; MIPS32-AE-NOT: andi
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; MIPS32-AE-NOT: sra
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%3 = insertelement <8 x i16> %1, i16 %a4, i32 %2
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; MIPS32-AE-DAG: sll [[BIDX:\$[0-9]+]], [[IDX]], 1
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; MIPS32-AE-DAG: sld.b [[R1]], [[R1]]{{\[}}[[BIDX]]]
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; MIPS32-AE-DAG: insert.h [[R1]][0], $4
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; MIPS32-AE-DAG: neg [[NIDX:\$[0-9]+]], [[BIDX]]
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; MIPS32-AE-DAG: sld.b [[R1]], [[R1]]{{\[}}[[NIDX]]]
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store <8 x i16> %3, <8 x i16>* @v8i16
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; MIPS32-AE-DAG: st.h [[R1]]
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ret void
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; MIPS32-AE: .size insert_v8i16_vidx
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}
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define void @insert_v4i32_vidx(i32 %a) nounwind {
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; MIPS32-AE: insert_v4i32_vidx:
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%1 = load <4 x i32>* @v4i32
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; MIPS32-AE-DAG: ld.w [[R1:\$w[0-9]+]],
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%2 = load i32* @i32
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; MIPS32-AE-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)(
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; MIPS32-AE-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]])
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; MIPS32-AE-NOT: andi
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; MIPS32-AE-NOT: sra
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%3 = insertelement <4 x i32> %1, i32 %a, i32 %2
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; MIPS32-AE-DAG: sll [[BIDX:\$[0-9]+]], [[IDX]], 2
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; MIPS32-AE-DAG: sld.b [[R1]], [[R1]]{{\[}}[[BIDX]]]
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; MIPS32-AE-DAG: insert.w [[R1]][0], $4
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; MIPS32-AE-DAG: neg [[NIDX:\$[0-9]+]], [[BIDX]]
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; MIPS32-AE-DAG: sld.b [[R1]], [[R1]]{{\[}}[[NIDX]]]
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store <4 x i32> %3, <4 x i32>* @v4i32
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; MIPS32-AE-DAG: st.w [[R1]]
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ret void
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; MIPS32-AE: .size insert_v4i32_vidx
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}
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define void @insert_v2i64_vidx(i64 %a) nounwind {
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; MIPS32-AE: insert_v2i64_vidx:
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%1 = load <2 x i64>* @v2i64
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; MIPS32-AE-DAG: ld.w [[R1:\$w[0-9]+]],
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%2 = load i32* @i32
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; MIPS32-AE-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)(
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; MIPS32-AE-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]])
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; MIPS32-AE-NOT: andi
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; MIPS32-AE-NOT: sra
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%3 = insertelement <2 x i64> %1, i64 %a, i32 %2
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; TODO: This code could be a lot better but it works. The legalizer splits
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; 64-bit inserts into two 32-bit inserts because there is no i64 type on
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; MIPS32. The obvious optimisation is to perform both insert.w's at once while
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; the vector is rotated.
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; MIPS32-AE-DAG: sll [[BIDX:\$[0-9]+]], [[IDX]], 2
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; MIPS32-AE-DAG: sld.b [[R1]], [[R1]]{{\[}}[[BIDX]]]
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; MIPS32-AE-DAG: insert.w [[R1]][0], $4
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; MIPS32-AE-DAG: neg [[NIDX:\$[0-9]+]], [[BIDX]]
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; MIPS32-AE-DAG: sld.b [[R1]], [[R1]]{{\[}}[[NIDX]]]
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; MIPS32-AE-DAG: addiu [[IDX2:\$[0-9]+]], [[IDX]], 1
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; MIPS32-AE-DAG: sll [[BIDX:\$[0-9]+]], [[IDX2]], 2
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; MIPS32-AE-DAG: sld.b [[R1]], [[R1]]{{\[}}[[BIDX]]]
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; MIPS32-AE-DAG: insert.w [[R1]][0], $5
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; MIPS32-AE-DAG: neg [[NIDX:\$[0-9]+]], [[BIDX]]
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; MIPS32-AE-DAG: sld.b [[R1]], [[R1]]{{\[}}[[NIDX]]]
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store <2 x i64> %3, <2 x i64>* @v2i64
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; MIPS32-AE-DAG: st.w [[R1]]
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ret void
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; MIPS32-AE: .size insert_v2i64_vidx
|
||||
}
|
||||
|
||||
define void @truncstore() nounwind {
|
||||
; MIPS32-AE-LABEL: truncstore:
|
||||
|
||||
|
||||
@ -275,3 +275,55 @@ define void @insert_v2f64(double %a) nounwind {
|
||||
ret void
|
||||
; MIPS32: .size insert_v2f64
|
||||
}
|
||||
|
||||
define void @insert_v4f32_vidx(float %a) nounwind {
|
||||
; MIPS32-LABEL: insert_v4f32_vidx:
|
||||
|
||||
%1 = load <4 x float>* @v4f32
|
||||
; MIPS32-DAG: lw [[PTR_V:\$[0-9]+]], %got(v4f32)(
|
||||
; MIPS32-DAG: ld.w [[R1:\$w[0-9]+]], 0([[PTR_V]])
|
||||
|
||||
%2 = load i32* @i32
|
||||
; MIPS32-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)(
|
||||
; MIPS32-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]])
|
||||
|
||||
%3 = insertelement <4 x float> %1, float %a, i32 %2
|
||||
; float argument passed in $f12
|
||||
; MIPS32-DAG: sll [[BIDX:\$[0-9]+]], [[IDX]], 2
|
||||
; MIPS32-DAG: sld.b [[R1]], [[R1]]{{\[}}[[BIDX]]]
|
||||
; MIPS32-DAG: insve.w [[R1]][0], $w12[0]
|
||||
; MIPS32-DAG: neg [[NIDX:\$[0-9]+]], [[BIDX]]
|
||||
; MIPS32-DAG: sld.b [[R1]], [[R1]]{{\[}}[[NIDX]]]
|
||||
|
||||
store <4 x float> %3, <4 x float>* @v4f32
|
||||
; MIPS32-DAG: st.w [[R1]]
|
||||
|
||||
ret void
|
||||
; MIPS32: .size insert_v4f32_vidx
|
||||
}
|
||||
|
||||
define void @insert_v2f64_vidx(double %a) nounwind {
|
||||
; MIPS32-LABEL: insert_v2f64_vidx:
|
||||
|
||||
%1 = load <2 x double>* @v2f64
|
||||
; MIPS32-DAG: lw [[PTR_V:\$[0-9]+]], %got(v2f64)(
|
||||
; MIPS32-DAG: ld.d [[R1:\$w[0-9]+]], 0([[PTR_V]])
|
||||
|
||||
%2 = load i32* @i32
|
||||
; MIPS32-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)(
|
||||
; MIPS32-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]])
|
||||
|
||||
%3 = insertelement <2 x double> %1, double %a, i32 %2
|
||||
; double argument passed in $f12
|
||||
; MIPS32-DAG: sll [[BIDX:\$[0-9]+]], [[IDX]], 3
|
||||
; MIPS32-DAG: sld.b [[R1]], [[R1]]{{\[}}[[BIDX]]]
|
||||
; MIPS32-DAG: insve.d [[R1]][0], $w12[0]
|
||||
; MIPS32-DAG: neg [[NIDX:\$[0-9]+]], [[BIDX]]
|
||||
; MIPS32-DAG: sld.b [[R1]], [[R1]]{{\[}}[[NIDX]]]
|
||||
|
||||
store <2 x double> %3, <2 x double>* @v2f64
|
||||
; MIPS32-DAG: st.d [[R1]]
|
||||
|
||||
ret void
|
||||
; MIPS32: .size insert_v2f64_vidx
|
||||
}
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user