6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-09-24 23:28:41 +00:00
Code Issues Projects Releases Wiki Activity

Allow targets more controls on what nodes are scheduled by reg pressure, what for latency in hybrid mode.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104293 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
2010-05-20 23:26:43 +00:00
parent 0fe46d9b48
commit 1cc3984148
8 changed files with 52 additions and 16 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
View File

@@ -1256,8 +1256,10 @@ bool src_ls_rr_sort::operator()(const SUnit *left, const SUnit *right) const {
}
bool hybrid_ls_rr_sort::operator()(const SUnit *left, const SUnit *right) const{
bool LStall = SPQ->getCurCycle() < left->getHeight();
bool RStall = SPQ->getCurCycle() < right->getHeight();
bool LStall = left->SchedulingPref == Sched::Latency &&
SPQ->getCurCycle() < left->getHeight();
bool RStall = right->SchedulingPref == Sched::Latency &&
SPQ->getCurCycle() < right->getHeight();
// If scheduling one of the node will cause a pipeline stall, delay it.
// If scheduling either one of the node will cause a pipeline stall, sort them
// according to their height.