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PR7586: Make sure we don't claim that unknown bits are actually known in the

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ISD::AND case of TargetLowering::SimplifyDemandedBits.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110019 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Eli Friedman 2010-08-02 04:42:25 +00:00
parent e28015c02c
commit 1d17d199a4
1 changed files with 2 additions and 3 deletions
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5
lib/CodeGen/SelectionDAG/TargetLowering.cpp
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@ -1497,11 +1497,10 @@ bool TargetLowering::SimplifyDemandedBits(SDValue Op,
// present in the input.
APInt NewBits =
APInt::getHighBitsSet(BitWidth,
BitWidth - EVT.getScalarType().getSizeInBits()) &
NewMask;
BitWidth - EVT.getScalarType().getSizeInBits());
// If none of the extended bits are demanded, eliminate the sextinreg.
if (NewBits == 0)
if ((NewBits & NewMask) == 0)
return TLO.CombineTo(Op, Op.getOperand(0));
APInt InSignBit = APInt::getSignBit(EVT.getScalarType().getSizeInBits());