mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-11-01 15:11:24 +00:00
comment out a bunch of parallel store patterns that apparently
can't match or just have no testcases. Will remove after confirmation from dan that they really are dead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98930 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
parent
6b7c2cf5d4
commit
1d7dbd1716
@ -2224,7 +2224,7 @@ def : Pat<(parallel (X86add_flag GR64:$src1, i64immSExt32:$src2),
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def : Pat<(parallel (X86add_flag GR64:$src1, (loadi64 addr:$src2)),
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(implicit EFLAGS)),
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(ADD64rm GR64:$src1, addr:$src2)>;
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/*
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// Memory-Register Addition with EFLAGS result
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def : Pat<(parallel (store (X86add_flag (loadi64 addr:$dst), GR64:$src2),
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addr:$dst),
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@ -2239,6 +2239,7 @@ def : Pat<(parallel (store (X86add_flag (loadi64 addr:$dst),
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addr:$dst),
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(implicit EFLAGS)),
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(ADD64mi32 addr:$dst, i64immSExt32:$src2)>;
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*/
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// Register-Register Subtraction with EFLAGS result
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def : Pat<(parallel (X86sub_flag GR64:$src1, GR64:$src2),
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@ -2258,6 +2259,7 @@ def : Pat<(parallel (X86sub_flag GR64:$src1, i64immSExt32:$src2),
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(implicit EFLAGS)),
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(SUB64ri32 GR64:$src1, i64immSExt32:$src2)>;
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/*
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// Memory-Register Subtraction with EFLAGS result
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def : Pat<(parallel (store (X86sub_flag (loadi64 addr:$dst), GR64:$src2),
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addr:$dst),
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@ -2275,6 +2277,7 @@ def : Pat<(parallel (store (X86sub_flag (loadi64 addr:$dst),
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addr:$dst),
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(implicit EFLAGS)),
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(SUB64mi32 addr:$dst, i64immSExt32:$src2)>;
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*/
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// Register-Register Signed Integer Multiplication with EFLAGS result
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def : Pat<(parallel (X86smul_flag GR64:$src1, GR64:$src2),
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@ -2305,36 +2308,45 @@ def : Pat<(parallel (X86smul_flag (loadi64 addr:$src1), i64immSExt32:$src2),
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// INC and DEC with EFLAGS result. Note that these do not set CF.
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def : Pat<(parallel (X86inc_flag GR16:$src), (implicit EFLAGS)),
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(INC64_16r GR16:$src)>, Requires<[In64BitMode]>;
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/*
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def : Pat<(parallel (store (i16 (X86inc_flag (loadi16 addr:$dst))), addr:$dst),
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(implicit EFLAGS)),
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(INC64_16m addr:$dst)>, Requires<[In64BitMode]>;
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(INC64_16m addr:$dst)>, Requires<[In64BitMode]>;*/
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def : Pat<(parallel (X86dec_flag GR16:$src), (implicit EFLAGS)),
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(DEC64_16r GR16:$src)>, Requires<[In64BitMode]>;
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/*
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def : Pat<(parallel (store (i16 (X86dec_flag (loadi16 addr:$dst))), addr:$dst),
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(implicit EFLAGS)),
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(DEC64_16m addr:$dst)>, Requires<[In64BitMode]>;
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(DEC64_16m addr:$dst)>, Requires<[In64BitMode]>;*/
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def : Pat<(parallel (X86inc_flag GR32:$src), (implicit EFLAGS)),
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(INC64_32r GR32:$src)>, Requires<[In64BitMode]>;
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/*
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def : Pat<(parallel (store (i32 (X86inc_flag (loadi32 addr:$dst))), addr:$dst),
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(implicit EFLAGS)),
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(INC64_32m addr:$dst)>, Requires<[In64BitMode]>;
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(INC64_32m addr:$dst)>, Requires<[In64BitMode]>;*/
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def : Pat<(parallel (X86dec_flag GR32:$src), (implicit EFLAGS)),
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(DEC64_32r GR32:$src)>, Requires<[In64BitMode]>;
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/*
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def : Pat<(parallel (store (i32 (X86dec_flag (loadi32 addr:$dst))), addr:$dst),
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(implicit EFLAGS)),
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(DEC64_32m addr:$dst)>, Requires<[In64BitMode]>;
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*/
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def : Pat<(parallel (X86inc_flag GR64:$src), (implicit EFLAGS)),
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(INC64r GR64:$src)>;
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/*
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def : Pat<(parallel (store (i64 (X86inc_flag (loadi64 addr:$dst))), addr:$dst),
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(implicit EFLAGS)),
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(INC64m addr:$dst)>;
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*/
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def : Pat<(parallel (X86dec_flag GR64:$src), (implicit EFLAGS)),
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(DEC64r GR64:$src)>;
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/*
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def : Pat<(parallel (store (i64 (X86dec_flag (loadi64 addr:$dst))), addr:$dst),
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(implicit EFLAGS)),
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(DEC64m addr:$dst)>;
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*/
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// Register-Register Logical Or with EFLAGS result
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def : Pat<(parallel (X86or_flag GR64:$src1, GR64:$src2),
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@ -2355,6 +2367,7 @@ def : Pat<(parallel (X86or_flag GR64:$src1, (loadi64 addr:$src2)),
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(OR64rm GR64:$src1, addr:$src2)>;
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// Memory-Register Logical Or with EFLAGS result
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/*
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def : Pat<(parallel (store (X86or_flag (loadi64 addr:$dst), GR64:$src2),
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addr:$dst),
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(implicit EFLAGS)),
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@ -2367,6 +2380,7 @@ def : Pat<(parallel (store (X86or_flag (loadi64 addr:$dst), i64immSExt32:$src2),
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addr:$dst),
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(implicit EFLAGS)),
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(OR64mi32 addr:$dst, i64immSExt32:$src2)>;
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*/
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// Register-Register Logical XOr with EFLAGS result
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def : Pat<(parallel (X86xor_flag GR64:$src1, GR64:$src2),
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@ -2387,6 +2401,7 @@ def : Pat<(parallel (X86xor_flag GR64:$src1, (loadi64 addr:$src2)),
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(XOR64rm GR64:$src1, addr:$src2)>;
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// Memory-Register Logical XOr with EFLAGS result
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/*
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def : Pat<(parallel (store (X86xor_flag (loadi64 addr:$dst), GR64:$src2),
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addr:$dst),
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(implicit EFLAGS)),
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@ -2400,6 +2415,7 @@ def : Pat<(parallel (store (X86xor_flag (loadi64 addr:$dst),
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addr:$dst),
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(implicit EFLAGS)),
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(XOR64mi32 addr:$dst, i64immSExt32:$src2)>;
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*/
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// Register-Register Logical And with EFLAGS result
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def : Pat<(parallel (X86and_flag GR64:$src1, GR64:$src2),
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@ -2420,6 +2436,7 @@ def : Pat<(parallel (X86and_flag GR64:$src1, (loadi64 addr:$src2)),
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(AND64rm GR64:$src1, addr:$src2)>;
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// Memory-Register Logical And with EFLAGS result
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/*
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def : Pat<(parallel (store (X86and_flag (loadi64 addr:$dst), GR64:$src2),
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addr:$dst),
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(implicit EFLAGS)),
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@ -2433,6 +2450,7 @@ def : Pat<(parallel (store (X86and_flag (loadi64 addr:$dst),
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addr:$dst),
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(implicit EFLAGS)),
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(AND64mi32 addr:$dst, i64immSExt32:$src2)>;
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*/
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//===----------------------------------------------------------------------===//
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// X86-64 SSE Instructions
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@ -4784,6 +4784,7 @@ def : Pat<(parallel (X86add_flag GR32:$src1, i32immSExt8:$src2),
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(implicit EFLAGS)),
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(ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
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/*
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// Memory-Register Addition with EFLAGS result
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def : Pat<(parallel (store (X86add_flag (loadi8 addr:$dst), GR8:$src2),
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addr:$dst),
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@ -4819,6 +4820,7 @@ def : Pat<(parallel (store (X86add_flag (loadi32 addr:$dst), i32immSExt8:$src2),
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addr:$dst),
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(implicit EFLAGS)),
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(ADD32mi8 addr:$dst, i32immSExt8:$src2)>;
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*/
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// Register-Register Subtraction with EFLAGS result
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def : Pat<(parallel (X86sub_flag GR8:$src1, GR8:$src2),
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@ -4859,6 +4861,7 @@ def : Pat<(parallel (X86sub_flag GR32:$src1, i32immSExt8:$src2),
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(implicit EFLAGS)),
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(SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
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/*
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// Memory-Register Subtraction with EFLAGS result
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def : Pat<(parallel (store (X86sub_flag (loadi8 addr:$dst), GR8:$src2),
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addr:$dst),
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@ -4894,7 +4897,7 @@ def : Pat<(parallel (store (X86sub_flag (loadi32 addr:$dst), i32immSExt8:$src2),
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addr:$dst),
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(implicit EFLAGS)),
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(SUB32mi8 addr:$dst, i32immSExt8:$src2)>;
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*/
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// Register-Register Signed Integer Multiply with EFLAGS result
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def : Pat<(parallel (X86smul_flag GR16:$src1, GR16:$src2),
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@ -4954,36 +4957,40 @@ def : Pat<(parallel (X86smul_flag GR32:$src1, 2),
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// INC and DEC with EFLAGS result. Note that these do not set CF.
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def : Pat<(parallel (X86inc_flag GR8:$src), (implicit EFLAGS)),
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(INC8r GR8:$src)>;
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/*
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def : Pat<(parallel (store (i8 (X86inc_flag (loadi8 addr:$dst))), addr:$dst),
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(implicit EFLAGS)),
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(INC8m addr:$dst)>;
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*/
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def : Pat<(parallel (X86dec_flag GR8:$src), (implicit EFLAGS)),
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(DEC8r GR8:$src)>;
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def : Pat<(parallel (store (i8 (X86dec_flag (loadi8 addr:$dst))), addr:$dst),
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/*def : Pat<(parallel (store (i8 (X86dec_flag (loadi8 addr:$dst))), addr:$dst),
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(implicit EFLAGS)),
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(DEC8m addr:$dst)>;
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(DEC8m addr:$dst)>;*/
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def : Pat<(parallel (X86inc_flag GR16:$src), (implicit EFLAGS)),
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(INC16r GR16:$src)>, Requires<[In32BitMode]>;
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/*
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def : Pat<(parallel (store (i16 (X86inc_flag (loadi16 addr:$dst))), addr:$dst),
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(implicit EFLAGS)),
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(INC16m addr:$dst)>, Requires<[In32BitMode]>;
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(INC16m addr:$dst)>, Requires<[In32BitMode]>;*/
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def : Pat<(parallel (X86dec_flag GR16:$src), (implicit EFLAGS)),
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(DEC16r GR16:$src)>, Requires<[In32BitMode]>;
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/*
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def : Pat<(parallel (store (i16 (X86dec_flag (loadi16 addr:$dst))), addr:$dst),
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(implicit EFLAGS)),
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(DEC16m addr:$dst)>, Requires<[In32BitMode]>;
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(DEC16m addr:$dst)>, Requires<[In32BitMode]>;*/
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def : Pat<(parallel (X86inc_flag GR32:$src), (implicit EFLAGS)),
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(INC32r GR32:$src)>, Requires<[In32BitMode]>;
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def : Pat<(parallel (store (i32 (X86inc_flag (loadi32 addr:$dst))), addr:$dst),
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/*def : Pat<(parallel (store (i32 (X86inc_flag (loadi32 addr:$dst))), addr:$dst),
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(implicit EFLAGS)),
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(INC32m addr:$dst)>, Requires<[In32BitMode]>;
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(INC32m addr:$dst)>, Requires<[In32BitMode]>;*/
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def : Pat<(parallel (X86dec_flag GR32:$src), (implicit EFLAGS)),
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(DEC32r GR32:$src)>, Requires<[In32BitMode]>;
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def : Pat<(parallel (store (i32 (X86dec_flag (loadi32 addr:$dst))), addr:$dst),
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/*def : Pat<(parallel (store (i32 (X86dec_flag (loadi32 addr:$dst))), addr:$dst),
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(implicit EFLAGS)),
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(DEC32m addr:$dst)>, Requires<[In32BitMode]>;
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(DEC32m addr:$dst)>, Requires<[In32BitMode]>;*/
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// Register-Register Or with EFLAGS result
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def : Pat<(parallel (X86or_flag GR8:$src1, GR8:$src2),
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@ -5023,7 +5030,7 @@ def : Pat<(parallel (X86or_flag GR16:$src1, i16immSExt8:$src2),
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def : Pat<(parallel (X86or_flag GR32:$src1, i32immSExt8:$src2),
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(implicit EFLAGS)),
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(OR32ri8 GR32:$src1, i32immSExt8:$src2)>;
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/*
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// Memory-Register Or with EFLAGS result
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def : Pat<(parallel (store (X86or_flag (loadi8 addr:$dst), GR8:$src2),
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addr:$dst),
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@ -5059,6 +5066,7 @@ def : Pat<(parallel (store (X86or_flag (loadi32 addr:$dst), i32immSExt8:$src2),
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addr:$dst),
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(implicit EFLAGS)),
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(OR32mi8 addr:$dst, i32immSExt8:$src2)>;
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*/
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// Register-Register XOr with EFLAGS result
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def : Pat<(parallel (X86xor_flag GR8:$src1, GR8:$src2),
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@ -5099,6 +5107,7 @@ def : Pat<(parallel (X86xor_flag GR32:$src1, i32immSExt8:$src2),
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(implicit EFLAGS)),
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(XOR32ri8 GR32:$src1, i32immSExt8:$src2)>;
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/*
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// Memory-Register XOr with EFLAGS result
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def : Pat<(parallel (store (X86xor_flag (loadi8 addr:$dst), GR8:$src2),
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addr:$dst),
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@ -5134,6 +5143,7 @@ def : Pat<(parallel (store (X86xor_flag (loadi32 addr:$dst), i32immSExt8:$src2),
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addr:$dst),
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(implicit EFLAGS)),
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(XOR32mi8 addr:$dst, i32immSExt8:$src2)>;
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*/
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// Register-Register And with EFLAGS result
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def : Pat<(parallel (X86and_flag GR8:$src1, GR8:$src2),
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@ -5174,6 +5184,7 @@ def : Pat<(parallel (X86and_flag GR32:$src1, i32immSExt8:$src2),
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(implicit EFLAGS)),
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(AND32ri8 GR32:$src1, i32immSExt8:$src2)>;
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/*
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// Memory-Register And with EFLAGS result
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def : Pat<(parallel (store (X86and_flag (loadi8 addr:$dst), GR8:$src2),
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addr:$dst),
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@ -5209,6 +5220,7 @@ def : Pat<(parallel (store (X86and_flag (loadi32 addr:$dst), i32immSExt8:$src2),
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addr:$dst),
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(implicit EFLAGS)),
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(AND32mi8 addr:$dst, i32immSExt8:$src2)>;
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*/
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// -disable-16bit support.
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def : Pat<(truncstorei16 (i16 imm:$src), addr:$dst),
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