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ARM "rrx" shift operands do not have an immediate. PR7790.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110292 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bob Wilson
2010-08-05 00:34:42 +00:00
parent ca356afe09
commit 1d9125a6ff
3 changed files with 22 additions and 24 deletions
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17
lib/Target/ARM/ARMAsmPrinter.cpp
View File

@@ -468,14 +468,12 @@ void ARMAsmPrinter::printSORegOperand(const MachineInstr *MI, int Op,
O << getRegisterName(MO1.getReg());
// Print the shift opc.
O << ", "
<< ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm()))
<< " ";
ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO3.getImm());
O << ", " << ARM_AM::getShiftOpcStr(ShOpc);
if (MO2.getReg()) {
O << getRegisterName(MO2.getReg());
O << ' ' << getRegisterName(MO2.getReg());
assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
} else {
} else if (ShOpc != ARM_AM::rrx) {
O << " #" << ARM_AM::getSORegOffset(MO3.getImm());
}
}
@@ -767,11 +765,10 @@ void ARMAsmPrinter::printT2SOOperand(const MachineInstr *MI, int OpNum,
O << getRegisterName(Reg);
// Print the shift opc.
O << ", "
<< ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO2.getImm()))
<< " ";
assert(MO2.isImm() && "Not a valid t2_so_reg value!");
ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO2.getImm());
O << ", " << ARM_AM::getShiftOpcStr(ShOpc);
if (ShOpc != ARM_AM::rrx)
O << " #" << ARM_AM::getSORegOffset(MO2.getImm());
}

17
lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp
View File

@@ -278,14 +278,12 @@ void ARMInstPrinter::printSORegOperand(const MCInst *MI, unsigned OpNum,
O << getRegisterName(MO1.getReg());
// Print the shift opc.
O << ", "
<< ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm()))
<< ' ';
ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO3.getImm());
O << ", " << ARM_AM::getShiftOpcStr(ShOpc);
if (MO2.getReg()) {
O << getRegisterName(MO2.getReg());
O << ' ' << getRegisterName(MO2.getReg());
assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
} else {
} else if (ShOpc != ARM_AM::rrx) {
O << " #" << ARM_AM::getSORegOffset(MO3.getImm());
}
}
@@ -669,11 +667,10 @@ void ARMInstPrinter::printT2SOOperand(const MCInst *MI, unsigned OpNum,
O << getRegisterName(Reg);
// Print the shift opc.
O << ", "
<< ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO2.getImm()))
<< " ";
assert(MO2.isImm() && "Not a valid t2_so_reg value!");
ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO2.getImm());
O << ", " << ARM_AM::getShiftOpcStr(ShOpc);
if (ShOpc != ARM_AM::rrx)
O << " #" << ARM_AM::getSORegOffset(MO2.getImm());
}

4
test/MC/Disassembler/arm-tests.txt
View File

@@ -42,6 +42,10 @@
# CHECK: mvnpls r7, #245, 2
0xf5 0x71 0xf0 0x53
# CHECK-NOT: orr r7, r8, r7, rrx #0
# CHECK: orr r7, r8, r7, rrx
0x67 0x70 0x88 0xe1
# CHECK: pkhbt r8, r9, r10, lsl #4
0x1a 0x82 0x89 0xe6