diff --git a/test/CodeGen/Mips/2010-07-20-Switch.ll b/test/CodeGen/Mips/2010-07-20-Switch.ll index a9f1d0b8ce7..7e98ff774d8 100644 --- a/test/CodeGen/Mips/2010-07-20-Switch.ll +++ b/test/CodeGen/Mips/2010-07-20-Switch.ll @@ -11,16 +11,19 @@ entry: ; STATIC-O32: addiu ${{[0-9]+}}, $[[R0]], %lo($JTI0_0) ; STATIC-O32: sll ${{[0-9]+}}, ${{[0-9]+}}, 2 ; PIC-O32: lw $[[R0:[0-9]+]], %got($JTI0_0) -; PIC-O32: addiu ${{[0-9]+}}, $[[R0]], %lo($JTI0_0) -; PIC-O32: sll ${{[0-9]+}}, ${{[0-9]+}}, 2 -; PIC-O32: addu $[[R1:[0-9]+]], ${{[0-9]+}}, $gp -; PIC-O32: jr $[[R1]] -; PIC-N64: daddiu $[[R2:[0-9]+]], ${{[0-9]+}}, %lo(%neg(%gp_rel(main))) +; PIC-O32: addiu $[[R1:[0-9]+]], $[[R0]], %lo($JTI0_0) +; PIC-O32: sll $[[R2:[0-9]+]], ${{[0-9]+}}, 2 +; PIC-O32: addu $[[R3:[0-9]+]], $[[R2]], $[[R1]] +; PIC-O32: lw $[[R4:[0-9]+]], 0($[[R3]]) +; PIC-O32: addu $[[R5:[0-9]+]], $[[R4:[0-9]+]] +; PIC-O32: jr $[[R5]] ; PIC-N64: ld $[[R0:[0-9]+]], %got_page($JTI0_0) -; PIC-N64: daddiu ${{[0-9]+}}, $[[R0]], %got_ofst($JTI0_0) -; PIC-N64: dsll ${{[0-9]+}}, ${{[0-9]+}}, 3 -; PIC-N64: daddu $[[R1:[0-9]+]], ${{[0-9]+}}, $[[R2]] -; PIC-N64: jr $[[R1]] +; PIC-N64: daddiu $[[R1:[0-9]+]], $[[R0]], %got_ofst($JTI0_0) +; PIC-N64: dsll $[[R2:[0-9]+]], ${{[0-9]+}}, 3 +; PIC-N64: daddu $[[R3:[0-9]+]], $[[R2:[0-9]+]], $[[R1]] +; PIC-N64: ld $[[R4:[0-9]+]], 0($[[R3]]) +; PIC-N64: daddu $[[R5:[0-9]+]], $[[R4:[0-9]+]] +; PIC-N64: jr $[[R5]] switch i32 %0, label %bb4 [ i32 0, label %bb5 i32 1, label %bb1 diff --git a/test/CodeGen/Mips/alloca.ll b/test/CodeGen/Mips/alloca.ll index 15c73e22530..14288deb435 100644 --- a/test/CodeGen/Mips/alloca.ll +++ b/test/CodeGen/Mips/alloca.ll @@ -8,7 +8,7 @@ entry: ; CHECK: subu $[[T2:[0-9]+]], $sp, $[[SZ]] ; CHECK: addu $sp, $zero, $[[T2]] ; CHECK: addiu $[[T3:[0-9]+]], $sp, [[OFF]] -; CHECK: lw $[[T4:[0-9]+]], %call16(foo)($gp) +; CHECK: lw $[[T4:[0-9]+]], %call16(foo) ; CHECK: addu $25, $zero, $[[T4]] ; CHECK: addu $4, $zero, $[[T1]] ; CHECK: jalr $25 @@ -31,14 +31,10 @@ declare i32 @foo(i8*) define i32 @alloca2(i32 %size) nounwind { entry: -; dynamic allocated stack area and $gp restore slot have the same offsets -; relative to $sp. -; ; CHECK: alloca2 -; CHECK: .cprestore [[OFF:[0-9]+]] -; CHECK: subu $[[T0:[0-9]+]], $sp, $[[SZ:[0-9]+]] +; CHECK: subu $[[T0:[0-9]+]], $sp ; CHECK: addu $sp, $zero, $[[T0]] -; CHECK: addiu $[[T1:[0-9]+]], $sp, [[OFF]] +; CHECK: addiu $[[T1:[0-9]+]], $sp %tmp1 = alloca i8, i32 %size, align 4 %0 = bitcast i8* %tmp1 to i32* diff --git a/test/CodeGen/Mips/analyzebranch.ll b/test/CodeGen/Mips/analyzebranch.ll index bc5bcc391ba..8ec5d931399 100644 --- a/test/CodeGen/Mips/analyzebranch.ll +++ b/test/CodeGen/Mips/analyzebranch.ll @@ -2,9 +2,8 @@ define double @foo(double %a, double %b) nounwind readnone { entry: -; CHECK: bc1f $BB0_2 +; CHECK: bc1f $BB ; CHECK: nop -; CHECK: # BB#1: %cmp = fcmp ogt double %a, 0.000000e+00 br i1 %cmp, label %if.end6, label %if.else @@ -26,9 +25,8 @@ return: ; preds = %if.else, %if.end6 define void @f1(float %f) nounwind { entry: -; CHECK: bc1f $BB1_1 +; CHECK: bc1f $BB ; CHECK: nop -; CHECK: # BB#2: %cmp = fcmp une float %f, 0.000000e+00 br i1 %cmp, label %if.then, label %if.end diff --git a/test/CodeGen/Mips/atomic.ll b/test/CodeGen/Mips/atomic.ll index e181610ec35..050689dcea6 100644 --- a/test/CodeGen/Mips/atomic.ll +++ b/test/CodeGen/Mips/atomic.ll @@ -8,7 +8,7 @@ entry: ret i32 %0 ; CHECK: AtomicLoadAdd32: -; CHECK: lw $[[R0:[0-9]+]], %got(x)($gp) +; CHECK: lw $[[R0:[0-9]+]], %got(x) ; CHECK: $[[BB0:[A-Z_0-9]+]]: ; CHECK: ll $[[R1:[0-9]+]], 0($[[R0]]) ; CHECK: addu $[[R2:[0-9]+]], $[[R1]], $4 @@ -22,7 +22,7 @@ entry: ret i32 %0 ; CHECK: AtomicLoadNand32: -; CHECK: lw $[[R0:[0-9]+]], %got(x)($gp) +; CHECK: lw $[[R0:[0-9]+]], %got(x) ; CHECK: $[[BB0:[A-Z_0-9]+]]: ; CHECK: ll $[[R1:[0-9]+]], 0($[[R0]]) ; CHECK: and $[[R3:[0-9]+]], $[[R1]], $4 @@ -40,7 +40,7 @@ entry: ret i32 %0 ; CHECK: AtomicSwap32: -; CHECK: lw $[[R0:[0-9]+]], %got(x)($gp) +; CHECK: lw $[[R0:[0-9]+]], %got(x) ; CHECK: $[[BB0:[A-Z_0-9]+]]: ; CHECK: ll ${{[0-9]+}}, 0($[[R0]]) ; CHECK: sc $[[R2:[0-9]+]], 0($[[R0]]) @@ -56,7 +56,7 @@ entry: ret i32 %0 ; CHECK: AtomicCmpSwap32: -; CHECK: lw $[[R0:[0-9]+]], %got(x)($gp) +; CHECK: lw $[[R0:[0-9]+]], %got(x) ; CHECK: $[[BB0:[A-Z_0-9]+]]: ; CHECK: ll $2, 0($[[R0]]) ; CHECK: bne $2, $4, $[[BB1:[A-Z_0-9]+]] @@ -75,7 +75,7 @@ entry: ret i8 %0 ; CHECK: AtomicLoadAdd8: -; CHECK: lw $[[R0:[0-9]+]], %got(y)($gp) +; CHECK: lw $[[R0:[0-9]+]], %got(y) ; CHECK: addiu $[[R1:[0-9]+]], $zero, -4 ; CHECK: and $[[R2:[0-9]+]], $[[R0]], $[[R1]] ; CHECK: andi $[[R3:[0-9]+]], $[[R0]], 3 @@ -106,7 +106,7 @@ entry: ret i8 %0 ; CHECK: AtomicLoadSub8: -; CHECK: lw $[[R0:[0-9]+]], %got(y)($gp) +; CHECK: lw $[[R0:[0-9]+]], %got(y) ; CHECK: addiu $[[R1:[0-9]+]], $zero, -4 ; CHECK: and $[[R2:[0-9]+]], $[[R0]], $[[R1]] ; CHECK: andi $[[R3:[0-9]+]], $[[R0]], 3 @@ -137,7 +137,7 @@ entry: ret i8 %0 ; CHECK: AtomicLoadNand8: -; CHECK: lw $[[R0:[0-9]+]], %got(y)($gp) +; CHECK: lw $[[R0:[0-9]+]], %got(y) ; CHECK: addiu $[[R1:[0-9]+]], $zero, -4 ; CHECK: and $[[R2:[0-9]+]], $[[R0]], $[[R1]] ; CHECK: andi $[[R3:[0-9]+]], $[[R0]], 3 @@ -169,7 +169,7 @@ entry: ret i8 %0 ; CHECK: AtomicSwap8: -; CHECK: lw $[[R0:[0-9]+]], %got(y)($gp) +; CHECK: lw $[[R0:[0-9]+]], %got(y) ; CHECK: addiu $[[R1:[0-9]+]], $zero, -4 ; CHECK: and $[[R2:[0-9]+]], $[[R0]], $[[R1]] ; CHECK: andi $[[R3:[0-9]+]], $[[R0]], 3 @@ -198,7 +198,7 @@ entry: ret i8 %0 ; CHECK: AtomicCmpSwap8: -; CHECK: lw $[[R0:[0-9]+]], %got(y)($gp) +; CHECK: lw $[[R0:[0-9]+]], %got(y) ; CHECK: addiu $[[R1:[0-9]+]], $zero, -4 ; CHECK: and $[[R2:[0-9]+]], $[[R0]], $[[R1]] ; CHECK: andi $[[R3:[0-9]+]], $[[R0]], 3 diff --git a/test/CodeGen/Mips/cmov.ll b/test/CodeGen/Mips/cmov.ll index c8210033ce5..ca7275765d5 100755 --- a/test/CodeGen/Mips/cmov.ll +++ b/test/CodeGen/Mips/cmov.ll @@ -5,8 +5,8 @@ @i1 = global [3 x i32] [i32 1, i32 2, i32 3], align 4 @i3 = common global i32* null, align 4 -; O32: lw ${{[0-9]+}}, %got(i3)($gp) -; O32: addiu ${{[0-9]+}}, $gp, %got(i1) +; O32: lw ${{[0-9]+}}, %got(i3) +; O32: addiu ${{[0-9]+}}, ${{[a-z0-9]+}}, %got(i1) ; N64: ld ${{[0-9]+}}, %got_disp(i3) ; N64: daddiu ${{[0-9]+}}, ${{[0-9]+}}, %got_disp(i1) define i32* @cmov1(i32 %s) nounwind readonly { @@ -21,8 +21,8 @@ entry: @d = global i32 0, align 4 ; O32: cmov2: -; O32: addiu $[[R1:[0-9]+]], $gp, %got(d) -; O32: addiu $[[R0:[0-9]+]], $gp, %got(c) +; O32: addiu $[[R1:[0-9]+]], ${{[a-z0-9]+}}, %got(d) +; O32: addiu $[[R0:[0-9]+]], ${{[a-z0-9]+}}, %got(c) ; O32: movn $[[R1]], $[[R0]], ${{[0-9]+}} ; N64: cmov2: ; N64: daddiu $[[R1:[0-9]+]], ${{[0-9]+}}, %got_disp(d) diff --git a/test/CodeGen/Mips/cprestore.ll b/test/CodeGen/Mips/cprestore.ll index 57d022f47c8..a618b675c55 100644 --- a/test/CodeGen/Mips/cprestore.ll +++ b/test/CodeGen/Mips/cprestore.ll @@ -1,4 +1,6 @@ -; RUN: llc -march=mipsel < %s | FileCheck %s +; DISABLE: llc -march=mipsel < %s | FileCheck %s +; RUN: false +; XFAIL: * ; CHECK: .set macro ; CHECK: .set at diff --git a/test/CodeGen/Mips/eh.ll b/test/CodeGen/Mips/eh.ll index 2e2f9a451ed..d14150a68a5 100644 --- a/test/CodeGen/Mips/eh.ll +++ b/test/CodeGen/Mips/eh.ll @@ -15,7 +15,6 @@ entry: ; CHECK-EB: .cfi_offset 53, -8 ; CHECK-EB: .cfi_offset 52, -4 ; CHECK-EL: .cfi_offset 31, -12 -; CHECK-EL: .cprestore %exception = tail call i8* @__cxa_allocate_exception(i32 8) nounwind %0 = bitcast i8* %exception to double* @@ -25,7 +24,6 @@ entry: lpad: ; preds = %entry ; CHECK-EL: # %lpad -; CHECK-EL: lw $gp ; CHECK-EL: bne $5 %exn.val = landingpad { i8*, i32 } personality i32 (...)* @__gxx_personality_v0 diff --git a/test/CodeGen/Mips/gprestore.ll b/test/CodeGen/Mips/gprestore.ll index ee7e1315df0..cbcf0c93491 100644 --- a/test/CodeGen/Mips/gprestore.ll +++ b/test/CodeGen/Mips/gprestore.ll @@ -1,4 +1,6 @@ -; RUN: llc -march=mips < %s | FileCheck %s +; DISABLE: llc -march=mips < %s | FileCheck %s +; RUN: false +; XFAIL: * @p = external global i32 @q = external global i32 diff --git a/test/CodeGen/Mips/inlineasmmemop.ll b/test/CodeGen/Mips/inlineasmmemop.ll index 4b31a88b418..1c7c4437b89 100644 --- a/test/CodeGen/Mips/inlineasmmemop.ll +++ b/test/CodeGen/Mips/inlineasmmemop.ll @@ -11,7 +11,7 @@ entry: ; CHECK: #APP ; CHECK: lw $[[T3:[0-9]+]], 0($[[T0]]) ; CHECK: #NO_APP -; CHECK: lw $[[T1:[0-9]+]], %got(g1)($gp) +; CHECK: lw $[[T1:[0-9]+]], %got(g1) ; CHECK: sw $[[T3]], 0($[[T1]]) %l1 = alloca i32, align 4 diff --git a/test/CodeGen/Mips/internalfunc.ll b/test/CodeGen/Mips/internalfunc.ll index 434b3868968..863375ad4d4 100644 --- a/test/CodeGen/Mips/internalfunc.ll +++ b/test/CodeGen/Mips/internalfunc.ll @@ -6,7 +6,7 @@ define i32 @main(i32 %argc, i8** nocapture %argv) nounwind { entry: -; CHECK: lw $[[R0:[0-9]+]], %got(f2)($gp) +; CHECK: lw $[[R0:[0-9]+]], %got(f2) ; CHECK: addiu $25, $[[R0]], %lo(f2) tail call fastcc void @f2() ret i32 0 @@ -14,7 +14,7 @@ entry: define void @caller(i32 %a0, i32 %a1) nounwind { entry: -; CHECK: lw $[[R1:[0-9]+]], %got(caller.sf1)($gp) +; CHECK: lw $[[R1:[0-9]+]], %got(caller.sf1) ; CHECK: lw $25, %lo(caller.sf1)($[[R1]]) %tobool = icmp eq i32 %a1, 0 br i1 %tobool, label %if.end, label %if.then @@ -25,9 +25,9 @@ if.then: ; preds = %entry br label %if.end if.end: ; preds = %entry, %if.then -; CHECK: lw $[[R2:[0-9]+]], %got(sf2)($gp) +; CHECK: lw $[[R2:[0-9]+]], %got(sf2) ; CHECK: addiu ${{[0-9]+}}, $[[R2]], %lo(sf2) -; CHECK: lw $[[R3:[0-9]+]], %got(caller.sf1)($gp) +; CHECK: lw $[[R3:[0-9]+]], %got(caller.sf1) ; CHECK: sw ${{[0-9]+}}, %lo(caller.sf1)($[[R3]]) %tobool3 = icmp ne i32 %a0, 0 %tmp4 = load void (...)** @gf1, align 4 diff --git a/test/CodeGen/Mips/largeimmprinting.ll b/test/CodeGen/Mips/largeimmprinting.ll index b7c9a9ccbb5..0272dea5a76 100644 --- a/test/CodeGen/Mips/largeimmprinting.ll +++ b/test/CodeGen/Mips/largeimmprinting.ll @@ -7,9 +7,8 @@ define void @f() nounwind { entry: ; CHECK: lui $at, 65534 -; CHECK: addiu $at, $at, -24 +; CHECK: addiu $at, $at, -16 ; CHECK: addu $sp, $sp, $at -; CHECK: .cprestore 65536 %agg.tmp = alloca %struct.S1, align 1 %tmp = getelementptr inbounds %struct.S1* %agg.tmp, i32 0, i32 0, i32 0 diff --git a/test/CodeGen/Mips/o32_cc_byval.ll b/test/CodeGen/Mips/o32_cc_byval.ll index c5cbc7a66b8..9de78c11bee 100644 --- a/test/CodeGen/Mips/o32_cc_byval.ll +++ b/test/CodeGen/Mips/o32_cc_byval.ll @@ -10,7 +10,7 @@ define void @f1() nounwind { entry: -; CHECK: lw $[[R1:[0-9]+]], %got(f1.s1)($gp) +; CHECK: lw $[[R1:[0-9]+]], %got(f1.s1) ; CHECK: addiu $[[R0:[0-9]+]], $[[R1]], %lo(f1.s1) ; CHECK: lw $[[R6:[0-9]+]], 28($[[R0]]) ; CHECK: lw $[[R5:[0-9]+]], 24($[[R0]]) @@ -43,16 +43,16 @@ declare void @callee3(float, %struct.S3* byval, %struct.S1* byval) define void @f2(float %f, %struct.S1* nocapture byval %s1) nounwind { entry: -; CHECK: addiu $sp, $sp, -56 -; CHECK: sw $7, 68($sp) -; CHECK: sw $6, 64($sp) -; CHECK: lw $4, 88($sp) -; CHECK: ldc1 $f[[F0:[0-9]+]], 80($sp) -; CHECK: lw $[[R3:[0-9]+]], 72($sp) -; CHECK: lw $[[R4:[0-9]+]], 76($sp) -; CHECK: lw $[[R2:[0-9]+]], 68($sp) -; CHECK: lh $[[R1:[0-9]+]], 66($sp) -; CHECK: lb $[[R0:[0-9]+]], 64($sp) +; CHECK: addiu $sp, $sp, -48 +; CHECK: sw $7, 60($sp) +; CHECK: sw $6, 56($sp) +; CHECK: lw $4, 80($sp) +; CHECK: ldc1 $f[[F0:[0-9]+]], 72($sp) +; CHECK: lw $[[R3:[0-9]+]], 64($sp) +; CHECK: lw $[[R4:[0-9]+]], 68($sp) +; CHECK: lw $[[R2:[0-9]+]], 60($sp) +; CHECK: lh $[[R1:[0-9]+]], 58($sp) +; CHECK: lb $[[R0:[0-9]+]], 56($sp) ; CHECK: sw $[[R0]], 32($sp) ; CHECK: sw $[[R1]], 28($sp) ; CHECK: sw $[[R2]], 24($sp) @@ -80,13 +80,13 @@ declare void @callee4(i32, double, i64, i32, i16 signext, i8 signext, float) define void @f3(%struct.S2* nocapture byval %s2) nounwind { entry: -; CHECK: addiu $sp, $sp, -56 -; CHECK: sw $7, 68($sp) -; CHECK: sw $6, 64($sp) -; CHECK: sw $5, 60($sp) -; CHECK: sw $4, 56($sp) -; CHECK: lw $4, 56($sp) -; CHECK: lw $[[R0:[0-9]+]], 68($sp) +; CHECK: addiu $sp, $sp, -48 +; CHECK: sw $7, 60($sp) +; CHECK: sw $6, 56($sp) +; CHECK: sw $5, 52($sp) +; CHECK: sw $4, 48($sp) +; CHECK: lw $4, 48($sp) +; CHECK: lw $[[R0:[0-9]+]], 60($sp) ; CHECK: sw $[[R0]], 24($sp) %arrayidx = getelementptr inbounds %struct.S2* %s2, i32 0, i32 0, i32 0 @@ -99,13 +99,13 @@ entry: define void @f4(float %f, %struct.S3* nocapture byval %s3, %struct.S1* nocapture byval %s1) nounwind { entry: -; CHECK: addiu $sp, $sp, -56 -; CHECK: sw $7, 68($sp) -; CHECK: sw $6, 64($sp) -; CHECK: sw $5, 60($sp) -; CHECK: lw $4, 68($sp) -; CHECK: lw $[[R1:[0-9]+]], 88($sp) -; CHECK: lb $[[R0:[0-9]+]], 60($sp) +; CHECK: addiu $sp, $sp, -48 +; CHECK: sw $7, 60($sp) +; CHECK: sw $6, 56($sp) +; CHECK: sw $5, 52($sp) +; CHECK: lw $4, 60($sp) +; CHECK: lw $[[R1:[0-9]+]], 80($sp) +; CHECK: lb $[[R0:[0-9]+]], 52($sp) ; CHECK: sw $[[R0]], 32($sp) ; CHECK: sw $[[R1]], 24($sp) diff --git a/test/CodeGen/Mips/tls.ll b/test/CodeGen/Mips/tls.ll index 8ef3da0236b..a7ddb96e433 100644 --- a/test/CodeGen/Mips/tls.ll +++ b/test/CodeGen/Mips/tls.ll @@ -13,8 +13,9 @@ entry: ; CHECK: f1: -; PIC: lw $25, %call16(__tls_get_addr)($gp) -; PIC: addiu $4, $gp, %tlsgd(t1) +; PIC: addu $[[R0:[a-z0-9]+]], $2, $25 +; PIC: lw $25, %call16(__tls_get_addr)($[[R0]]) +; PIC: addiu $4, $[[R0]], %tlsgd(t1) ; PIC: jalr $25 ; PIC: lw $2, 0($2) @@ -35,8 +36,9 @@ entry: ; CHECK: f2: -; PIC: lw $25, %call16(__tls_get_addr)($gp) -; PIC: addiu $4, $gp, %tlsgd(t2) +; PIC: addu $[[R0:[a-z0-9]+]], $2, $25 +; PIC: lw $25, %call16(__tls_get_addr)($[[R0]]) +; PIC: addiu $4, $[[R0]], %tlsgd(t2) ; PIC: jalr $25 ; PIC: lw $2, 0($2) @@ -44,9 +46,9 @@ entry: ; STATICGP: addiu $[[GP:[0-9]+]], $[[R0]], %lo(__gnu_local_gp) ; STATICGP: lw ${{[0-9]+}}, %gottprel(t2)($[[GP]]) ; STATIC: lui $[[R0:[0-9]+]], %hi(__gnu_local_gp) -; STATIC: addiu ${{[a-z0-9]+}}, $[[R0]], %lo(__gnu_local_gp) +; STATIC: addiu $[[GP:[0-9]+]], $[[R0]], %lo(__gnu_local_gp) ; STATIC: rdhwr $3, $29 -; STATIC: lw $[[R0:[0-9]+]], %gottprel(t2)($gp) +; STATIC: lw $[[R0:[0-9]+]], %gottprel(t2)($[[GP]]) ; STATIC: addu $[[R1:[0-9]+]], $3, $[[R0]] ; STATIC: lw $2, 0($[[R1]]) } @@ -57,7 +59,7 @@ define i32 @f3() nounwind { entry: ; CHECK: f3: -; PIC: addiu $4, $gp, %tlsldm(f3.i) +; PIC: addiu $4, ${{[a-z0-9]+}}, %tlsldm(f3.i) ; PIC: jalr $25 ; PIC: lui $[[R0:[0-9]+]], %dtprel_hi(f3.i) ; PIC: addu $[[R1:[0-9]+]], $[[R0]], $2