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Implement ISD::TRAP support on PPC

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54644 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Nate Begeman 2008-08-11 17:36:31 +00:00
parent 1e7f7865eb
commit 1db3c92306
4 changed files with 18 additions and 2 deletions
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5
lib/Target/PowerPC/PPCISelLowering.cpp
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@ -183,9 +183,12 @@ PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
setOperationAction(ISD::JumpTable, MVT::i64, Custom);
// RET must be custom lowered, to meet ABI requirements
// RET must be custom lowered, to meet ABI requirements.
setOperationAction(ISD::RET , MVT::Other, Custom);
// TRAP is legal.
setOperationAction(ISD::TRAP, MVT::Other, Legal);
// VASTART needs to be custom lowered to use the VarArgsFrameIndex
setOperationAction(ISD::VASTART , MVT::Other, Custom);

11
lib/Target/PowerPC/PPCInstrFormats.td
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@ -298,6 +298,17 @@ class XForm_17<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
let Inst{31} = 0;
}
class XForm_24<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
InstrItinClass itin, list<dag> pattern>
: I<opcode, OOL, IOL, asmstr, itin> {
let Pattern = pattern;
let Inst{6-10} = 31;
let Inst{11-15} = 0;
let Inst{16-20} = 0;
let Inst{21-30} = xo;
let Inst{31} = 0;
}
class XForm_25<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
InstrItinClass itin, list<dag> pattern>
: XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {

3
lib/Target/PowerPC/PPCInstrInfo.td
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@ -575,6 +575,9 @@ def STWCX : XForm_1<31, 150, (outs), (ins GPRC:$rS, memrr:$dst),
[(PPCstcx GPRC:$rS, xoaddr:$dst)]>,
isDOT;
let isBarrier = 1, hasCtrlDep = 1 in
def TRAP : XForm_24<31, 4, (outs), (ins), "trap", LdStGeneral, [(trap)]>;
//===----------------------------------------------------------------------===//
// PPC32 Load Instructions.
//

1
lib/Target/PowerPC/README.txt
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@ -3,7 +3,6 @@
TODO:
* gpr0 allocation
* implement do-loop -> bdnz transform
* Implement __builtin_trap (ISD::TRAP) as 'tw 31, 0, 0' aka 'trap'.
* lmw/stmw pass a la arm load store optimizer for prolog/epilog
===-------------------------------------------------------------------------===