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Change LowerFP_TO_SINT to create the specific code it needs instead of

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unconditionally creating an i64 bitcast.  With the future legalizer
design, operation legalization can't introduce new nodes with illegal
types.

This fixes the rest of olden on ppc32.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43005 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2007-10-15 20:14:52 +00:00
parent 87c8935fd5
commit 1de7c1dd6f
1 changed files with 11 additions and 4 deletions
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15
lib/Target/PowerPC/PPCISelLowering.cpp
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@ -2028,7 +2028,7 @@ static SDOperand LowerSELECT_CC(SDOperand Op, SelectionDAG &DAG) {
DAG.getNode(ISD::FNEG, MVT::f64, LHS), TV, FV);
}
SDOperand Cmp;
SDOperand Cmp;
switch (CC) {
default: break; // SETUO etc aren't handled by fsel.
case ISD::SETULT:
@ -2081,10 +2081,17 @@ static SDOperand LowerFP_TO_SINT(SDOperand Op, SelectionDAG &DAG) {
}
// Convert the FP value to an int value through memory.
SDOperand Bits = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Tmp);
SDOperand FIPtr = DAG.CreateStackTemporary(MVT::f64);
// Emit a store to the stack slot.
SDOperand Chain = DAG.getStore(DAG.getEntryNode(), Tmp, FIPtr, NULL, 0);
// Result is a load from the stack slot. If loading 4 bytes, make sure to
// add in a bias.
if (Op.getValueType() == MVT::i32)
Bits = DAG.getNode(ISD::TRUNCATE, MVT::i32, Bits);
return Bits;
FIPtr = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr,
DAG.getConstant(4, FIPtr.getValueType()));
return DAG.getLoad(Op.getValueType(), Chain, FIPtr, NULL, 0);
}
static SDOperand LowerFP_ROUND_INREG(SDOperand Op, SelectionDAG &DAG) {