diff --git a/lib/Bitcode/Reader/BitcodeReader.cpp b/lib/Bitcode/Reader/BitcodeReader.cpp
index a82892063b7..ebfca09c491 100644
--- a/lib/Bitcode/Reader/BitcodeReader.cpp
+++ b/lib/Bitcode/Reader/BitcodeReader.cpp
@@ -1337,30 +1337,17 @@ bool BitcodeReader::ParseFunctionBody(Function *F) {
     }
     
     case bitc::FUNC_CODE_INST_RET: // RET: [opty,opval<optional>]
-      {
-        unsigned Size = Record.size();
-        if (Size == 0) {
-          I = new ReturnInst();
-          break;
-        } else if (Size == 1) {
-          unsigned OpNum = 0;
-          Value *Op;
-          if (getValueTypePair(Record, OpNum, NextValueNo, Op) ||
-              OpNum != Record.size())
-            return Error("Invalid RET record");
-          I = new ReturnInst(Op);
-          break;
-        } else {
-          std::vector<Value *> Vs;
-          Value *Op;
-          unsigned OpNum = 0;
-          for (unsigned i = 0; i < Size; ++i) {
-            getValueTypePair(Record, OpNum, NextValueNo, Op);
-            Vs.push_back(Op);
-          }
-          I = new ReturnInst(Vs);
-          break;
-        }
+      if (Record.empty()) {
+        I = new ReturnInst();
+        break;
+      } else {
+        unsigned OpNum = 0;
+        Value *Op;
+        if (getValueTypePair(Record, OpNum, NextValueNo, Op) ||
+            OpNum != Record.size())
+          return Error("Invalid RET record");
+        I = new ReturnInst(Op);
+        break;
       }
     case bitc::FUNC_CODE_INST_BR: { // BR: [bb#, bb#, opval] or [bb#]
       if (Record.size() != 1 && Record.size() != 3)
diff --git a/lib/Bitcode/Writer/BitcodeWriter.cpp b/lib/Bitcode/Writer/BitcodeWriter.cpp
index 5de38b82156..9b2b93cfcea 100644
--- a/lib/Bitcode/Writer/BitcodeWriter.cpp
+++ b/lib/Bitcode/Writer/BitcodeWriter.cpp
@@ -747,23 +747,15 @@ static void WriteInstruction(const Instruction &I, unsigned InstID,
   case Instruction::GetResult:
     Code = bitc::FUNC_CODE_INST_GETRESULT;
     PushValueAndType(I.getOperand(0), InstID, Vals, VE);
-    Vals.push_back(cast<GetResultInst>(I).getIndex());
+    Vals.push_back(Log2_32(cast<GetResultInst>(I).getIndex())+1);
     break;
 
-  case Instruction::Ret: 
-    {
-      Code = bitc::FUNC_CODE_INST_RET;
-      unsigned NumOperands = I.getNumOperands();
-      if (NumOperands == 0)
-        AbbrevToUse = FUNCTION_INST_RET_VOID_ABBREV;
-      else if (NumOperands == 1) {
-        if (!PushValueAndType(I.getOperand(0), InstID, Vals, VE))
-          AbbrevToUse = FUNCTION_INST_RET_VAL_ABBREV;
-      } else {
-        for (unsigned i = 0, e = NumOperands; i != e; ++i)
-          PushValueAndType(I.getOperand(i), InstID, Vals, VE);
-      }
-    }
+  case Instruction::Ret:
+    Code = bitc::FUNC_CODE_INST_RET;
+    if (!I.getNumOperands())
+      AbbrevToUse = FUNCTION_INST_RET_VOID_ABBREV;
+    else if (!PushValueAndType(I.getOperand(0), InstID, Vals, VE))
+      AbbrevToUse = FUNCTION_INST_RET_VAL_ABBREV;
     break;
   case Instruction::Br:
     Code = bitc::FUNC_CODE_INST_BR;
diff --git a/test/Assembler/2008-02-20-MultipleReturnValue.ll b/test/Assembler/2008-02-20-MultipleReturnValue.ll
index 5b2ed7e8f48..f84ceef293b 100644
--- a/test/Assembler/2008-02-20-MultipleReturnValue.ll
+++ b/test/Assembler/2008-02-20-MultipleReturnValue.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | opt -verify | llvm-dis | llvm-as -disable-output
+; RUN: llvm-as < %s -disable-output
 
 define {i32, i8} @foo(i32 %p) {
   ret i32 1, i8 2