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Sparc: No functionality change. Cleanup whitespaces, comment formatting etc.,

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183243 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Venkatraman Govindaraju
2013-06-04 18:33:25 +00:00
parent 5a57dbef33
commit 1e06bcbd63
19 changed files with 157 additions and 154 deletions
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32
lib/Target/Sparc/DelaySlotFiller.cpp
View File

@@ -115,7 +115,7 @@ bool Filler::runOnMachineBasicBlock(MachineBasicBlock &MBB) {
continue;
}
//If MI has no delay slot, skip
// If MI has no delay slot, skip.
if (!MI->hasDelaySlot())
continue;
@@ -165,7 +165,7 @@ Filler::findDelayInstr(MachineBasicBlock &MBB,
if (J->getOpcode() == SP::RESTORErr
|| J->getOpcode() == SP::RESTOREri) {
//change retl to ret
// change retl to ret.
slot->setDesc(TII->get(SP::RET));
return J;
}
@@ -364,15 +364,15 @@ static bool combineRestoreADD(MachineBasicBlock::iterator RestoreMI,
if (reg < SP::I0 || reg > SP::I7)
return false;
//Erase RESTORE
// Erase RESTORE.
RestoreMI->eraseFromParent();
//Change ADD to RESTORE
// Change ADD to RESTORE.
AddMI->setDesc(TII->get((AddMI->getOpcode() == SP::ADDrr)
? SP::RESTORErr
: SP::RESTOREri));
//map the destination register
// Map the destination register.
AddMI->getOperand(0).setReg(reg - SP::I0 + SP::O0);
return true;
@@ -392,7 +392,7 @@ static bool combineRestoreOR(MachineBasicBlock::iterator RestoreMI,
if (reg < SP::I0 || reg > SP::I7)
return false;
//check whether it is a copy
// check whether it is a copy.
if (OrMI->getOpcode() == SP::ORrr
&& OrMI->getOperand(1).getReg() != SP::G0
&& OrMI->getOperand(2).getReg() != SP::G0)
@@ -403,15 +403,15 @@ static bool combineRestoreOR(MachineBasicBlock::iterator RestoreMI,
&& (!OrMI->getOperand(2).isImm() || OrMI->getOperand(2).getImm() != 0))
return false;
//Erase RESTORE
// Erase RESTORE.
RestoreMI->eraseFromParent();
//Change OR to RESTORE
// Change OR to RESTORE.
OrMI->setDesc(TII->get((OrMI->getOpcode() == SP::ORrr)
? SP::RESTORErr
: SP::RESTOREri));
//map the destination register
// Map the destination register.
OrMI->getOperand(0).setReg(reg - SP::I0 + SP::O0);
return true;
@@ -435,11 +435,11 @@ static bool combineRestoreSETHIi(MachineBasicBlock::iterator RestoreMI,
int64_t imm = SetHiMI->getOperand(1).getImm();
//is it a 3 bit immediate?
// Is it a 3 bit immediate?
if (!isInt<3>(imm))
return false;
//make it a 13 bit immediate
// Make it a 13 bit immediate.
imm = (imm << 10) & 0x1FFF;
assert(RestoreMI->getOpcode() == SP::RESTORErr);
@@ -451,7 +451,7 @@ static bool combineRestoreSETHIi(MachineBasicBlock::iterator RestoreMI,
RestoreMI->getOperand(2).ChangeToImmediate(imm);
//Erase the original SETHI
// Erase the original SETHI.
SetHiMI->eraseFromParent();
return true;
@@ -460,11 +460,11 @@ static bool combineRestoreSETHIi(MachineBasicBlock::iterator RestoreMI,
bool Filler::tryCombineRestoreWithPrevInst(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI)
{
//No previous instruction
// No previous instruction.
if (MBBI == MBB.begin())
return false;
//asssert that MBBI is "restore %g0, %g0, %g0"
// assert that MBBI is a "restore %g0, %g0, %g0".
assert(MBBI->getOpcode() == SP::RESTORErr
&& MBBI->getOperand(0).getReg() == SP::G0
&& MBBI->getOperand(1).getReg() == SP::G0
@@ -472,7 +472,7 @@ bool Filler::tryCombineRestoreWithPrevInst(MachineBasicBlock &MBB,
MachineBasicBlock::iterator PrevInst = MBBI; --PrevInst;
//Cannot combine with a delay filler
// It cannot combine with a delay filler.
if (isDelayFiller(MBB, PrevInst))
return false;
@@ -484,6 +484,6 @@ bool Filler::tryCombineRestoreWithPrevInst(MachineBasicBlock &MBB,
case SP::ORri: return combineRestoreOR(MBBI, PrevInst, TII); break;
case SP::SETHIi: return combineRestoreSETHIi(MBBI, PrevInst, TII); break;
}
//Cannot combine with the previous instruction
// It cannot combine with the previous instruction.
return false;
}

3
lib/Target/Sparc/LLVMBuild.txt
View File

@@ -28,5 +28,6 @@ has_asmprinter = 1
type = Library
name = SparcCodeGen
parent = Sparc
required_libraries = AsmPrinter CodeGen Core MC SelectionDAG SparcDesc SparcInfo Support Target
required_libraries = AsmPrinter CodeGen Core MC SelectionDAG SparcDesc
SparcInfo Support Target
add_to_library_groups = Sparc

8
lib/Target/Sparc/SparcFrameLowering.cpp
View File

@@ -130,7 +130,7 @@ void SparcFrameLowering::emitEpilogue(MachineFunction &MF,
}
bool SparcFrameLowering::hasReservedCallFrame(const MachineFunction &MF) const {
//Reserve call frame if there are no variable sized objects on the stack
// Reserve call frame if there are no variable sized objects on the stack.
return !MF.getFrameInfo()->hasVarSizedObjects();
}
@@ -174,17 +174,17 @@ void SparcFrameLowering::remapRegsForLeafProc(MachineFunction &MF) const {
MachineRegisterInfo &MRI = MF.getRegInfo();
//remap %i[0-7] to %o[0-7]
// Remap %i[0-7] to %o[0-7].
for (unsigned reg = SP::I0; reg <= SP::I7; ++reg) {
if (!MRI.isPhysRegUsed(reg))
continue;
unsigned mapped_reg = (reg - SP::I0 + SP::O0);
assert(!MRI.isPhysRegUsed(mapped_reg));
//Replace I register with O register
// Replace I register with O register.
MRI.replaceRegWith(reg, mapped_reg);
//mark the reg unused.
// Mark the reg unused.
MRI.setPhysRegUnused(reg);
}

19
lib/Target/Sparc/SparcISelLowering.cpp
View File

@@ -40,7 +40,7 @@ static bool CC_Sparc_Assign_SRet(unsigned &ValNo, MVT &ValVT,
{
assert (ArgFlags.isSRet());
//Assign SRet argument
// Assign SRet argument.
State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
0,
LocVT, LocInfo));
@@ -54,18 +54,18 @@ static bool CC_Sparc_Assign_f64(unsigned &ValNo, MVT &ValVT,
static const uint16_t RegList[] = {
SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
};
//Try to get first reg
// Try to get first reg.
if (unsigned Reg = State.AllocateReg(RegList, 6)) {
State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
} else {
//Assign whole thing in stack
// Assign whole thing in stack.
State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
State.AllocateStack(8,4),
LocVT, LocInfo));
return true;
}
//Try to get second reg
// Try to get second reg.
if (unsigned Reg = State.AllocateReg(RegList, 6))
State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
else
@@ -351,7 +351,7 @@ LowerFormalArguments_32(SDValue Chain,
CCValAssign &VA = ArgLocs[i];
if (i == 0 && Ins[i].Flags.isSRet()) {
//Get SRet from [%fp+64]
// Get SRet from [%fp+64].
int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, 64, true);
SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
SDValue Arg = DAG.getLoad(MVT::i32, dl, Chain, FIPtr,
@@ -470,7 +470,7 @@ LowerFormalArguments_32(SDValue Chain,
}
if (MF.getFunction()->hasStructRetAttr()) {
//Copy the SRet Argument to SRetReturnReg
// Copy the SRet Argument to SRetReturnReg.
SparcMachineFunctionInfo *SFI = MF.getInfo<SparcMachineFunctionInfo>();
unsigned Reg = SFI->getSRetReturnReg();
if (!Reg) {
@@ -1398,7 +1398,8 @@ const char *SparcTargetLowering::getTargetNodeName(unsigned Opcode) const {
/// isMaskedValueZeroForTargetNode - Return true if 'Op & Mask' is known to
/// be zero. Op is expected to be a target specific node. Used by DAG
/// combiner.
void SparcTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
void SparcTargetLowering::computeMaskedBitsForTargetNode
(const SDValue Op,
APInt &KnownZero,
APInt &KnownOne,
const SelectionDAG &DAG,
@@ -1625,7 +1626,7 @@ static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG,
MachineFunction &MF = DAG.getMachineFunction();
SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>();
//Need frame address to find the address of VarArgsFrameIndex
// Need frame address to find the address of VarArgsFrameIndex.
MF.getFrameInfo()->setFrameAddressIsTaken(true);
// vastart just stores the address of the VarArgsFrameIndex slot into the
@@ -1734,7 +1735,7 @@ static SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) {
if (depth == 0)
RetAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, RetReg, VT);
else {
//Need frame address to find return address of the caller
// Need frame address to find return address of the caller.
MFI->setFrameAddressIsTaken(true);
// flush first to make sure the windowed registers' values are in stack

3
lib/Target/Sparc/SparcInstrFormats.td
View File

@@ -7,7 +7,8 @@
//
//===----------------------------------------------------------------------===//
class InstSP<dag outs, dag ins, string asmstr, list<dag> pattern> : Instruction {
class InstSP<dag outs, dag ins, string asmstr, list<dag> pattern>
: Instruction {
field bits<32> Inst;
let Namespace = "SP";

12
lib/Target/Sparc/SparcInstrInfo.cpp
View File

@@ -141,15 +141,15 @@ bool SparcInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
if (I->isDebugValue())
continue;
//When we see a non-terminator, we are done
// When we see a non-terminator, we are done.
if (!isUnpredicatedTerminator(I))
break;
//Terminator is not a branch
// Terminator is not a branch.
if (!I->isBranch())
return true;
//Handle Unconditional branches
// Handle Unconditional branches.
if (I->getOpcode() == SP::BA) {
UnCondBrIter = I;
@@ -178,7 +178,7 @@ bool SparcInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
unsigned Opcode = I->getOpcode();
if (Opcode != SP::BCOND && Opcode != SP::FBCOND)
return true; //Unknown Opcode
return true; // Unknown Opcode.
SPCC::CondCodes BranchCode = (SPCC::CondCodes)I->getOperand(1).getImm();
@@ -221,8 +221,8 @@ bool SparcInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
Cond.push_back(MachineOperand::CreateImm(BranchCode));
continue;
}
//FIXME: Handle subsequent conditional branches
//For now, we can't handle multiple conditional branches
// FIXME: Handle subsequent conditional branches.
// For now, we can't handle multiple conditional branches.
return true;
}
return false;

2
lib/Target/Sparc/SparcInstrInfo.td
View File

@@ -516,7 +516,7 @@ let isBarrier = 1 in
"ba $dst",
[(br bb:$dst)]>;
//Indirect Branch
// Indirect branch instructions.
let isTerminator = 1, isBarrier = 1,
hasDelaySlot = 1, isBranch =1,
isIndirectBranch = 1 in {