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[mips] Fix instruction definitions that were incorrectly marked as code-gen-only.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188690 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Akira Hatanaka 2013-08-19 19:08:03 +00:00
parent 630d175667
commit 1e09ed1389
2 changed files with 10 additions and 6 deletions
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15
lib/Target/Mips/MipsCondMov.td
View File

@ -148,15 +148,17 @@ let Predicates = [NotFP64bit, HasStdEnc] in {
CMov_I_F_FM<19, 17>;
}
let Predicates = [IsFP64bit, HasStdEnc], isCodeGenOnly = 1 in {
let Predicates = [IsFP64bit, HasStdEnc], DecoderNamespace = "Mips64" in {
def MOVZ_I_D64 : CMov_I_F_FT<"movz.d", GPR32Opnd, FGR64Opnd, IIFmove>,
CMov_I_F_FM<18, 17>;
def MOVZ_I64_D64 : CMov_I_F_FT<"movz.d", GPR64Opnd, FGR64Opnd,
IIFmove>, CMov_I_F_FM<18, 17>;
def MOVN_I_D64 : CMov_I_F_FT<"movn.d", GPR32Opnd, FGR64Opnd, IIFmove>,
CMov_I_F_FM<19, 17>;
def MOVN_I64_D64 : CMov_I_F_FT<"movn.d", GPR64Opnd, FGR64Opnd,
IIFmove>, CMov_I_F_FM<19, 17>;
let isCodeGenOnly = 1 in {
def MOVZ_I64_D64 : CMov_I_F_FT<"movz.d", GPR64Opnd, FGR64Opnd,
IIFmove>, CMov_I_F_FM<18, 17>;
def MOVN_I64_D64 : CMov_I_F_FT<"movn.d", GPR64Opnd, FGR64Opnd,
IIFmove>, CMov_I_F_FM<19, 17>;
}
}
def MOVT_I : CMov_F_I_FT<"movt", GPR32Opnd, IIArith, MipsCMovFP_T>,
@ -184,7 +186,8 @@ let Predicates = [NotFP64bit, HasStdEnc] in {
def MOVF_D32 : CMov_F_F_FT<"movf.d", AFGR64Opnd, IIFmove, MipsCMovFP_F>,
CMov_F_F_FM<17, 0>;
}
let Predicates = [IsFP64bit, HasStdEnc], isCodeGenOnly = 1 in {
let Predicates = [IsFP64bit, HasStdEnc], DecoderNamespace = "Mips64" in {
def MOVT_D64 : CMov_F_F_FT<"movt.d", FGR64Opnd, IIFmove, MipsCMovFP_T>,
CMov_F_F_FM<17, 1>;
def MOVF_D64 : CMov_F_F_FT<"movf.d", FGR64Opnd, IIFmove, MipsCMovFP_F>,

1
test/MC/Mips/mips-fpu-instructions.s
View File

@ -1,4 +1,5 @@
# RUN: llvm-mc %s -triple=mipsel-unknown-linux -show-encoding -mcpu=mips32r2 | FileCheck %s
# RUN: llvm-mc %s -triple=mips64el-unknown-linux -show-encoding -mcpu=mips64r2 | FileCheck %s
# Check that the assembler can handle the documented syntax
# for FPU instructions.
#------------------------------------------------------------------------------