6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-07-06 01:24:35 +00:00
Code Issues Projects Releases Wiki Activity

Tidy up comment grammar.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179986 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach
2013-04-21 21:23:01 +00:00
parent 2c6b5a8d33
commit 1e48093df8
1 changed files with 2 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
View File

@ -1272,8 +1272,8 @@ SDValue DAGTypeLegalizer::SplitVecOp_STORE(StoreSDNode *N, unsigned OpNo) {
SDValue DAGTypeLegalizer::SplitVecOp_CONCAT_VECTORS(SDNode *N) { SDValue DAGTypeLegalizer::SplitVecOp_CONCAT_VECTORS(SDNode *N) {
DebugLoc DL = N->getDebugLoc(); DebugLoc DL = N->getDebugLoc();
// The input operands all must have the same type, and we know the result the // The input operands all must have the same type, and we know the result
// result type is valid. Convert this to a buildvector which extracts all the // type is valid. Convert this to a buildvector which extracts all the
// input elements. // input elements.
// TODO: If the input elements are power-two vectors, we could convert this to // TODO: If the input elements are power-two vectors, we could convert this to
// a new CONCAT_VECTORS node with elements that are half-wide. // a new CONCAT_VECTORS node with elements that are half-wide.