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Constify AArch64CollectLOH.cpp. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231969 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -279,7 +279,7 @@ static const SetOfMachineInstr *getUses(const InstrToInstrs *sets, unsigned reg,
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/// definition. It also consider definitions of ADRP instructions as uses and
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/// definition. It also consider definitions of ADRP instructions as uses and
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/// ignore other uses. The ADRPMode is used to collect the information for LHO
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/// ignore other uses. The ADRPMode is used to collect the information for LHO
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/// that involve ADRP operation only.
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/// that involve ADRP operation only.
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static void initReachingDef(MachineFunction &MF,
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static void initReachingDef(const MachineFunction &MF,
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InstrToInstrs *ColorOpToReachedUses,
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InstrToInstrs *ColorOpToReachedUses,
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BlockToInstrPerColor &Gen, BlockToRegSet &Kill,
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BlockToInstrPerColor &Gen, BlockToRegSet &Kill,
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BlockToSetOfInstrsPerColor &ReachableUses,
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BlockToSetOfInstrsPerColor &ReachableUses,
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@ -288,7 +288,7 @@ static void initReachingDef(MachineFunction &MF,
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const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
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const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
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unsigned NbReg = RegToId.size();
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unsigned NbReg = RegToId.size();
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for (MachineBasicBlock &MBB : MF) {
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for (const MachineBasicBlock &MBB : MF) {
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auto &BBGen = Gen[&MBB];
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auto &BBGen = Gen[&MBB];
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BBGen = make_unique<const MachineInstr *[]>(NbReg);
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BBGen = make_unique<const MachineInstr *[]>(NbReg);
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std::fill(BBGen.get(), BBGen.get() + NbReg, nullptr);
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std::fill(BBGen.get(), BBGen.get() + NbReg, nullptr);
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@ -382,7 +382,7 @@ static void initReachingDef(MachineFunction &MF,
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/// op.reachedUses
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/// op.reachedUses
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///
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///
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/// Out[bb] = Gen[bb] U (In[bb] - Kill[bb])
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/// Out[bb] = Gen[bb] U (In[bb] - Kill[bb])
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static void reachingDefAlgorithm(MachineFunction &MF,
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static void reachingDefAlgorithm(const MachineFunction &MF,
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InstrToInstrs *ColorOpToReachedUses,
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InstrToInstrs *ColorOpToReachedUses,
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BlockToSetOfInstrsPerColor &In,
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BlockToSetOfInstrsPerColor &In,
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BlockToSetOfInstrsPerColor &Out,
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BlockToSetOfInstrsPerColor &Out,
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@ -392,7 +392,7 @@ static void reachingDefAlgorithm(MachineFunction &MF,
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bool HasChanged;
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bool HasChanged;
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do {
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do {
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HasChanged = false;
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HasChanged = false;
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for (MachineBasicBlock &MBB : MF) {
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for (const MachineBasicBlock &MBB : MF) {
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unsigned CurReg;
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unsigned CurReg;
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for (CurReg = 0; CurReg < NbReg; ++CurReg) {
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for (CurReg = 0; CurReg < NbReg; ++CurReg) {
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SetOfMachineInstr &BBInSet = getSet(In, MBB, CurReg, NbReg);
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SetOfMachineInstr &BBInSet = getSet(In, MBB, CurReg, NbReg);
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@ -401,7 +401,7 @@ static void reachingDefAlgorithm(MachineFunction &MF,
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SetOfMachineInstr &BBOutSet = getSet(Out, MBB, CurReg, NbReg);
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SetOfMachineInstr &BBOutSet = getSet(Out, MBB, CurReg, NbReg);
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unsigned Size = BBOutSet.size();
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unsigned Size = BBOutSet.size();
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// In[bb][color] = U Out[bb.predecessors][color]
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// In[bb][color] = U Out[bb.predecessors][color]
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for (MachineBasicBlock *PredMBB : MBB.predecessors()) {
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for (const MachineBasicBlock *PredMBB : MBB.predecessors()) {
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SetOfMachineInstr &PredOutSet = getSet(Out, *PredMBB, CurReg, NbReg);
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SetOfMachineInstr &PredOutSet = getSet(Out, *PredMBB, CurReg, NbReg);
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BBInSet.insert(PredOutSet.begin(), PredOutSet.end());
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BBInSet.insert(PredOutSet.begin(), PredOutSet.end());
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}
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}
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@ -433,7 +433,7 @@ static void reachingDefAlgorithm(MachineFunction &MF,
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/// @p DummyOp.
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/// @p DummyOp.
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/// \pre ColorOpToReachedUses is an array of at least number of registers of
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/// \pre ColorOpToReachedUses is an array of at least number of registers of
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/// InstrToInstrs.
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/// InstrToInstrs.
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static void reachingDef(MachineFunction &MF,
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static void reachingDef(const MachineFunction &MF,
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InstrToInstrs *ColorOpToReachedUses,
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InstrToInstrs *ColorOpToReachedUses,
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const MapRegToId &RegToId, bool ADRPMode = false,
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const MapRegToId &RegToId, bool ADRPMode = false,
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const MachineInstr *DummyOp = nullptr) {
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const MachineInstr *DummyOp = nullptr) {
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@ -983,7 +983,7 @@ static void computeOthers(const InstrToInstrs &UseToDefs,
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/// Look for every register defined by potential LOHs candidates.
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/// Look for every register defined by potential LOHs candidates.
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/// Map these registers with dense id in @p RegToId and vice-versa in
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/// Map these registers with dense id in @p RegToId and vice-versa in
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/// @p IdToReg. @p IdToReg is populated only in DEBUG mode.
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/// @p IdToReg. @p IdToReg is populated only in DEBUG mode.
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static void collectInvolvedReg(MachineFunction &MF, MapRegToId &RegToId,
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static void collectInvolvedReg(const MachineFunction &MF, MapRegToId &RegToId,
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MapIdToReg &IdToReg,
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MapIdToReg &IdToReg,
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const TargetRegisterInfo *TRI) {
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const TargetRegisterInfo *TRI) {
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unsigned CurRegId = 0;
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unsigned CurRegId = 0;
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