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[mips] Make the branch nodes used in jump instructions a template parameter.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166337 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Akira Hatanaka
2012-10-19 21:11:03 +00:00
parent 58d1e3f72a
commit 1f027135a8
1 changed files with 21 additions and 10 deletions
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31
lib/Target/Mips/MipsInstrInfo.td
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@@ -179,6 +179,18 @@ class MipsPat<dag pattern, dag result> : Pat<pattern, result> {
let Predicates = [HasStandardEncoding]; let Predicates = [HasStandardEncoding];
} }
class IsBranch {
bit isBranch = 1;
}
class IsReturn {
bit isReturn = 1;
}
class IsCall {
bit isCall = 1;
}
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Instruction format superclass // Instruction format superclass
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
@@ -577,14 +589,12 @@ class SetCC_I<bits<6> op, string instr_asm, PatFrag cond_op, Operand Od,
IIAlu>; IIAlu>;
// Jump // Jump
class JumpFJ<bits<6> op, string instr_asm>: class JumpFJ<bits<6> op, string instr_asm, SDPatternOperator operator>:
FJ<op, (outs), (ins jmptarget:$target), FJ<op, (outs), (ins jmptarget:$target), !strconcat(instr_asm, "\t$target"),
!strconcat(instr_asm, "\t$target"), [(br bb:$target)], IIBranch> { [(operator bb:$target)], IIBranch> {
let isBranch=1;
let isTerminator=1; let isTerminator=1;
let isBarrier=1; let isBarrier=1;
let hasDelaySlot = 1; let hasDelaySlot = 1;
let Predicates = [RelocStatic, HasStandardEncoding];
let DecoderMethod = "DecodeJumpTarget"; let DecoderMethod = "DecodeJumpTarget";
let Defs = [AT]; let Defs = [AT];
} }
@@ -605,21 +615,21 @@ class UncondBranch<bits<6> op, string instr_asm>:
// Base class for indirect branch and return instruction classes. // Base class for indirect branch and return instruction classes.
let isTerminator=1, isBarrier=1, hasDelaySlot = 1 in let isTerminator=1, isBarrier=1, hasDelaySlot = 1 in
class JumpFR<RegisterClass RC, list<dag> pattern>: class JumpFR<RegisterClass RC, SDPatternOperator operator = null_frag>:
FR<0, 0x8, (outs), (ins RC:$rs), "jr\t$rs", pattern, IIBranch> { FR<0, 0x8, (outs), (ins RC:$rs), "jr\t$rs", [(operator RC:$rs)], IIBranch> {
let rt = 0; let rt = 0;
let rd = 0; let rd = 0;
let shamt = 0; let shamt = 0;
} }
// Indirect branch // Indirect branch
class IndirectBranch<RegisterClass RC>: JumpFR<RC, [(brind RC:$rs)]> { class IndirectBranch<RegisterClass RC>: JumpFR<RC, brind> {
let isBranch = 1; let isBranch = 1;
let isIndirectBranch = 1; let isIndirectBranch = 1;
} }
// Return instruction // Return instruction
class RetBase<RegisterClass RC>: JumpFR<RC, []> { class RetBase<RegisterClass RC>: JumpFR<RC> {
let isReturn = 1; let isReturn = 1;
let isCodeGenOnly = 1; let isCodeGenOnly = 1;
let hasCtrlDep = 1; let hasCtrlDep = 1;
@@ -984,7 +994,8 @@ def SC_P8 : SCBase<0x38, "sc", CPURegs, mem64>,
} }
/// Jump and Branch Instructions /// Jump and Branch Instructions
def J : JumpFJ<0x02, "j">; def J : JumpFJ<0x02, "j", br>,
Requires<[RelocStatic, HasStandardEncoding]>, IsBranch;
def JR : IndirectBranch<CPURegs>; def JR : IndirectBranch<CPURegs>;
def B : UncondBranch<0x04, "b">; def B : UncondBranch<0x04, "b">;
def BEQ : CBranch<0x04, "beq", seteq, CPURegs>; def BEQ : CBranch<0x04, "beq", seteq, CPURegs>;