From 1f05322d96319651c484a90eead4cebd6bd67ad3 Mon Sep 17 00:00:00 2001 From: Zoran Jovanovic Date: Thu, 15 May 2014 15:16:36 +0000 Subject: [PATCH] [mips][mips64r6] Add CLASS.fmt instructions Differential Revision: http://reviews.llvm.org/D3712 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208894 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Mips/Mips32r6InstrInfo.td | 14 +++++++++----- test/MC/Mips/mips32r6/valid.s | 2 ++ test/MC/Mips/mips64r6/valid.s | 2 ++ 3 files changed, 13 insertions(+), 5 deletions(-) diff --git a/lib/Target/Mips/Mips32r6InstrInfo.td b/lib/Target/Mips/Mips32r6InstrInfo.td index a2bcfe19179..41bbae105c1 100644 --- a/lib/Target/Mips/Mips32r6InstrInfo.td +++ b/lib/Target/Mips/Mips32r6InstrInfo.td @@ -92,6 +92,8 @@ class SELNEZ_D_ENC : COP1_3R_FM<0b010111, FIELD_FMT_D>; class RINT_S_ENC : COP1_2R_FM<0b011010, FIELD_FMT_S>; class RINT_D_ENC : COP1_2R_FM<0b011010, FIELD_FMT_D>; +class CLASS_S_ENC : COP1_2R_FM<0b011011, FIELD_FMT_S>; +class CLASS_D_ENC : COP1_2R_FM<0b011011, FIELD_FMT_D>; //===----------------------------------------------------------------------===// // @@ -210,15 +212,17 @@ class SELEQZ_D_DESC : SELEQNEZ_DESC_BASE<"seleqz.d", FGR64Opnd>; class SELNEZ_S_DESC : SELEQNEZ_DESC_BASE<"selnez.s", FGR32Opnd>; class SELNEZ_D_DESC : SELEQNEZ_DESC_BASE<"selnez.d", FGR64Opnd>; -class RINT_DESC_BASE { +class CLASS_RINT_DESC_BASE { dag OutOperandList = (outs FGROpnd:$fd); dag InOperandList = (ins FGROpnd:$fs); string AsmString = !strconcat(instr_asm, "\t$fd, $fs"); list Pattern = []; } -class RINT_S_DESC : RINT_DESC_BASE<"rint.s", FGR32Opnd>; -class RINT_D_DESC : RINT_DESC_BASE<"rint.d", FGR64Opnd>; +class RINT_S_DESC : CLASS_RINT_DESC_BASE<"rint.s", FGR32Opnd>; +class RINT_D_DESC : CLASS_RINT_DESC_BASE<"rint.d", FGR64Opnd>; +class CLASS_S_DESC : CLASS_RINT_DESC_BASE<"class.s", FGR32Opnd>; +class CLASS_D_DESC : CLASS_RINT_DESC_BASE<"class.d", FGR64Opnd>; //===----------------------------------------------------------------------===// // @@ -258,8 +262,8 @@ def BNEZALC; def BNEZC; def BNVC; def BOVC; -def CLASS_D; -def CLASS_S; +def CLASS_D : CLASS_D_ENC, CLASS_D_DESC, ISA_MIPS32R6; +def CLASS_S : CLASS_S_ENC, CLASS_S_DESC, ISA_MIPS32R6; def CMP_CC_D; def CMP_CC_S; def DIV : DIV_ENC, DIV_DESC, ISA_MIPS32R6; diff --git a/test/MC/Mips/mips32r6/valid.s b/test/MC/Mips/mips32r6/valid.s index 25f1a0cbdac..8b46d36d37b 100644 --- a/test/MC/Mips/mips32r6/valid.s +++ b/test/MC/Mips/mips32r6/valid.s @@ -34,3 +34,5 @@ selnez.d $f0, $f2, $f4 # CHECK: selnez.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x17] rint.s $f2, $f4 # CHECK: rint.s $f2, $f4 # encoding: [0x46,0x00,0x20,0x9a] rint.d $f2, $f4 # CHECK: rint.d $f2, $f4 # encoding: [0x46,0x20,0x20,0x9a] + class.s $f2, $f4 # CHECK: class.s $f2, $f4 # encoding: [0x46,0x00,0x20,0x9b] + class.d $f2, $f4 # CHECK: class.d $f2, $f4 # encoding: [0x46,0x20,0x20,0x9b] diff --git a/test/MC/Mips/mips64r6/valid.s b/test/MC/Mips/mips64r6/valid.s index fbda28262ec..b90c1ea0e0f 100644 --- a/test/MC/Mips/mips64r6/valid.s +++ b/test/MC/Mips/mips64r6/valid.s @@ -47,3 +47,5 @@ selnez.d $f0, $f2, $f4 # CHECK: selnez.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x17] rint.s $f2, $f4 # CHECK: rint.s $f2, $f4 # encoding: [0x46,0x00,0x20,0x9a] rint.d $f2, $f4 # CHECK: rint.d $f2, $f4 # encoding: [0x46,0x20,0x20,0x9a] + class.s $f2, $f4 # CHECK: class.s $f2, $f4 # encoding: [0x46,0x00,0x20,0x9b] + class.d $f2, $f4 # CHECK: class.d $f2, $f4 # encoding: [0x46,0x20,0x20,0x9b]