Partial support for Intel SHA Extensions (sha1rnds4)

Add basic assembly/disassembly support for the first Intel SHA
instruction 'sha1rnds4'. Also includes feature flag, and test cases.

Support for the remaining instructions will follow in a separate patch.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190611 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/X86/X86Subtarget.cpp

@@ -375,6 +375,10 @@ void X86Subtarget::AutoDetectSubtargetFeatures() {
         HasCDI = true;
         ToggleFeature(X86::FeatureCDI);
       }
+      if (IsIntel && ((EBX >> 29) & 0x1)) {
+        HasSHA = true;
+        ToggleFeature(X86::FeatureSHA);
+      }
     }
   }
 }
@@ -497,6 +501,7 @@ void X86Subtarget::initializeEnvironment() {
   HasCDI = false;
   HasPFI = false;
   HasADX = false;
+  HasSHA = false;
   HasPRFCHW = false;
   HasRDSEED = false;
   IsBTMemSlow = false;