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Specify an additional fixed bit in the PLD/PLDW/PLI register-register encoding.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138760 91177308-0d34-0410-b5e6-96231b3b80d8
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Owen Anderson 2011-08-29 20:42:00 +00:00
parent 6af6824eb4
commit 1f26758510
1 changed files with 1 additions and 0 deletions
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lib/Target/ARM/ARMInstrInfo.td
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@ -1507,6 +1507,7 @@ multiclass APreLoad<bits<1> read, bits<1> data, string opc> {
let Inst{19-16} = shift{16-13}; // Rn
let Inst{15-12} = 0b1111;
let Inst{11-0} = shift{11-0};
let Inst{4} = 0;
}
}