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Fix PR10059 and future variations by handling all register subclasses.

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Add TargetRegisterInfo::hasSubClassEq and use it to check for compatible
register classes instead of trying to list all register classes in
X86's getLoadStoreRegOpcode.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132398 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen 2011-06-01 15:32:10 +00:00
parent bdce3726e2
commit 1f9a09c614
2 changed files with 46 additions and 48 deletions
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12
include/llvm/Target/TargetRegisterInfo.h
View File

@ -182,6 +182,12 @@ public:
return false;
}
/// hasSubClassEq - Returns true if RC is a subclass of or equal to this
/// class.
bool hasSubClassEq(const TargetRegisterClass *RC) const {
return RC == this || hasSubClass(RC);
}
/// subclasses_begin / subclasses_end - Loop over all of the classes
/// that are proper subsets of this register class.
sc_iterator subclasses_begin() const {
@ -203,6 +209,12 @@ public:
return false;
}
/// hasSuperClassEq - Returns true if RC is a superclass of or equal to this
/// class.
bool hasSuperClassEq(const TargetRegisterClass *RC) const {
return RC == this || hasSuperClass(RC);
}
/// superclasses_begin / superclasses_end - Loop over all of the classes
/// that are proper supersets of this register class.
sc_iterator superclasses_begin() const {

82
lib/Target/X86/X86InstrInfo.cpp
View File

@ -2015,62 +2015,48 @@ static unsigned getLoadStoreRegOpcode(unsigned Reg,
bool isStackAligned,
const TargetMachine &TM,
bool load) {
switch (RC->getID()) {
switch (RC->getSize()) {
default:
llvm_unreachable("Unknown regclass");
case X86::GR64RegClassID:
case X86::GR64_ABCDRegClassID:
case X86::GR64_NOREXRegClassID:
case X86::GR64_NOREX_NOSPRegClassID:
case X86::GR64_NOSPRegClassID:
case X86::GR64_TCRegClassID:
case X86::GR64_TCW64RegClassID:
return load ? X86::MOV64rm : X86::MOV64mr;
case X86::GR32RegClassID:
case X86::GR32_ABCDRegClassID:
case X86::GR32_ADRegClassID:
case X86::GR32_NOREXRegClassID:
case X86::GR32_NOSPRegClassID:
case X86::GR32_TCRegClassID:
return load ? X86::MOV32rm : X86::MOV32mr;
case X86::GR16RegClassID:
case X86::GR16_ABCDRegClassID:
case X86::GR16_NOREXRegClassID:
return load ? X86::MOV16rm : X86::MOV16mr;
case X86::GR8RegClassID:
// Copying to or from a physical H register on x86-64 requires a NOREX
// move. Otherwise use a normal move.
if (isHReg(Reg) &&
TM.getSubtarget<X86Subtarget>().is64Bit())
return load ? X86::MOV8rm_NOREX : X86::MOV8mr_NOREX;
else
return load ? X86::MOV8rm : X86::MOV8mr;
case X86::GR8_ABCD_LRegClassID:
case X86::GR8_NOREXRegClassID:
return load ? X86::MOV8rm :X86::MOV8mr;
case X86::GR8_ABCD_HRegClassID:
llvm_unreachable("Unknown spill size");
case 1:
assert(X86::GR8RegClass.hasSubClassEq(RC) && "Unknown 1-byte regclass");
if (TM.getSubtarget<X86Subtarget>().is64Bit())
return load ? X86::MOV8rm_NOREX : X86::MOV8mr_NOREX;
else
return load ? X86::MOV8rm : X86::MOV8mr;
case X86::RFP80RegClassID:
// Copying to or from a physical H register on x86-64 requires a NOREX
// move. Otherwise use a normal move.
if (isHReg(Reg) || X86::GR8_ABCD_HRegClass.hasSubClassEq(RC))
return load ? X86::MOV8rm_NOREX : X86::MOV8mr_NOREX;
return load ? X86::MOV8rm : X86::MOV8mr;
case 2:
assert(X86::GR16RegClass.hasSubClassEq(RC) && "Unknown 2-byte regclass");
return load ? X86::MOV16rm : X86::MOV16mr;
case 4:
if (X86::GR32RegClass.hasSubClassEq(RC))
return load ? X86::MOV32rm : X86::MOV32mr;
if (X86::FR32RegClass.hasSubClassEq(RC))
return load ? X86::MOVSSrm : X86::MOVSSmr;
if (X86::RFP32RegClass.hasSubClassEq(RC))
return load ? X86::LD_Fp32m : X86::ST_Fp32m;
llvm_unreachable("Unknown 4-byte regclass");
case 8:
if (X86::GR64RegClass.hasSubClassEq(RC))
return load ? X86::MOV64rm : X86::MOV64mr;
if (X86::FR64RegClass.hasSubClassEq(RC))
return load ? X86::MOVSDrm : X86::MOVSDmr;
if (X86::VR64RegClass.hasSubClassEq(RC))
return load ? X86::MMX_MOVQ64rm : X86::MMX_MOVQ64mr;
if (X86::RFP64RegClass.hasSubClassEq(RC))
return load ? X86::LD_Fp64m : X86::ST_Fp64m;
llvm_unreachable("Unknown 8-byte regclass");
case 10:
assert(X86::RFP80RegClass.hasSubClassEq(RC) && "Unknown 10-byte regclass");
return load ? X86::LD_Fp80m : X86::ST_FpP80m;
case X86::RFP64RegClassID:
return load ? X86::LD_Fp64m : X86::ST_Fp64m;
case X86::RFP32RegClassID:
return load ? X86::LD_Fp32m : X86::ST_Fp32m;
case X86::FR32RegClassID:
return load ? X86::MOVSSrm : X86::MOVSSmr;
case X86::FR64RegClassID:
return load ? X86::MOVSDrm : X86::MOVSDmr;
case X86::VR128RegClassID:
case 16:
assert(X86::VR128RegClass.hasSubClassEq(RC) && "Unknown 16-byte regclass");
// If stack is realigned we can use aligned stores.
if (isStackAligned)
return load ? X86::MOVAPSrm : X86::MOVAPSmr;
else
return load ? X86::MOVUPSrm : X86::MOVUPSmr;
case X86::VR64RegClassID:
return load ? X86::MMX_MOVQ64rm : X86::MMX_MOVQ64mr;
}
}