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R600/SI: replace SI_V_CNDLT with a pattern

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It actually fixes quite a bunch of piglit tests.

This is a candidate for the mesa-stable branch.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175756 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Christian Konig 2013-02-21 15:17:32 +00:00
parent 664a061f81
commit 1fbb3b3ce5
3 changed files with 5 additions and 31 deletions
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22
lib/Target/R600/SIISelLowering.cpp
View File

@ -81,9 +81,6 @@ MachineBasicBlock * SITargetLowering::EmitInstrWithCustomInserter(
case AMDGPU::SI_WQM:
LowerSI_WQM(MI, *BB, I, MRI);
break;
case AMDGPU::SI_V_CNDLT:
LowerSI_V_CNDLT(MI, *BB, I, MRI);
break;
}
return BB;
}
@ -127,25 +124,6 @@ void SITargetLowering::LowerSI_INTERP(MachineInstr *MI, MachineBasicBlock &BB,
MI->eraseFromParent();
}
void SITargetLowering::LowerSI_V_CNDLT(MachineInstr *MI, MachineBasicBlock &BB,
MachineBasicBlock::iterator I, MachineRegisterInfo & MRI) const {
unsigned VCC = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
BuildMI(BB, I, BB.findDebugLoc(I),
TII->get(AMDGPU::V_CMP_GT_F32_e32),
VCC)
.addImm(0)
.addOperand(MI->getOperand(1));
BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::V_CNDMASK_B32_e32))
.addOperand(MI->getOperand(0))
.addOperand(MI->getOperand(3))
.addOperand(MI->getOperand(2))
.addReg(VCC);
MI->eraseFromParent();
}
EVT SITargetLowering::getSetCCResultType(EVT VT) const {
return MVT::i1;
}

2
lib/Target/R600/SIISelLowering.h
View File

@ -29,8 +29,6 @@ class SITargetLowering : public AMDGPUTargetLowering {
MachineBasicBlock::iterator I, MachineRegisterInfo & MRI) const;
void LowerSI_WQM(MachineInstr *MI, MachineBasicBlock &BB,
MachineBasicBlock::iterator I, MachineRegisterInfo & MRI) const;
void LowerSI_V_CNDLT(MachineInstr *MI, MachineBasicBlock &BB,
MachineBasicBlock::iterator I, MachineRegisterInfo & MRI) const;
SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;

12
lib/Target/R600/SIInstructions.td
View File

@ -990,13 +990,6 @@ def LOAD_CONST : AMDGPUShaderInst <
let usesCustomInserter = 1 in {
def SI_V_CNDLT : InstSI <
(outs VReg_32:$dst),
(ins VReg_32:$src0, VReg_32:$src1, VReg_32:$src2),
"SI_V_CNDLT $dst, $src0, $src1, $src2",
[(set VReg_32:$dst, (int_AMDGPU_cndlt VReg_32:$src0, VReg_32:$src1, VReg_32:$src2))]
>;
def SI_INTERP : InstSI <
(outs VReg_32:$dst),
(ins VReg_32:$i, VReg_32:$j, i32imm:$attr_chan, i32imm:$attr, SReg_32:$params),
@ -1086,6 +1079,11 @@ def SI_KILL : InstSI <
} // end IsCodeGenOnly, isPseudo
def : Pat<
(int_AMDGPU_cndlt VReg_32:$src0, VReg_32:$src1, VReg_32:$src2),
(V_CNDMASK_B32_e64 VReg_32:$src2, VReg_32:$src1, (V_CMP_GT_F32_e64 0, VReg_32:$src0))
>;
def : Pat <
(int_AMDGPU_kilp),
(SI_KILL (V_MOV_B32_e32 0xbf800000))