6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-12-12 09:20:42 +00:00
Code Issues Projects Releases Wiki Activity

WebAssembly: start instructions

Browse Source 
Summary:
* Add 64-bit address space feature.
* Rename SIMD feature to SIMD128.
* Handle single-thread model with an IR pass (same way ARM does).
* Rename generic processor to MVP, to follow design's lead.
* Add bleeding-edge processors, with all features included.
* Fix a few DEBUG_TYPE to match other backends.

Test Plan: ninja check

Reviewers: sunfish

Subscribers: jfb, llvm-commits

Differential Revision: http://reviews.llvm.org/D10880

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241211 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
JF Bastien
2015-07-01 23:41:25 +00:00
parent a1a323c637
commit 1ff585db47
8 changed files with 31 additions and 13 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
View File

@@ -12,4 +12,4 @@
//===----------------------------------------------------------------------===//
// TODO: Implement SIMD instructions.
// Note: use Requires<[HasSIMD]>.
// Note: use Requires<[HasSIMD128]>.