WebAssembly: start instructions

Summary:
* Add 64-bit address space feature.
* Rename SIMD feature to SIMD128.
* Handle single-thread model with an IR pass (same way ARM does).
* Rename generic processor to MVP, to follow design's lead.
* Add bleeding-edge processors, with all features included.
* Fix a few DEBUG_TYPE to match other backends.

Test Plan: ninja check

Reviewers: sunfish

Subscribers: jfb, llvm-commits

Differential Revision: http://reviews.llvm.org/D10880

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241211 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/WebAssembly/WebAssemblySubtarget.h

@@ -29,7 +29,7 @@
 namespace llvm {
 
 class WebAssemblySubtarget final : public WebAssemblyGenSubtargetInfo {
-  bool HasSIMD;
+  bool HasSIMD128;
 
   /// String name of used CPU.
   std::string CPUString;
@@ -66,7 +66,8 @@ public:
   bool useAA() const override { return true; }
 
   // Predicates used by WebAssemblyInstrInfo.td.
-  bool hasSIMD() const { return HasSIMD; }
+  bool hasAddr64() const { return TargetTriple.isArch64Bit(); }
+  bool hasSIMD128() const { return HasSIMD128; }
 
   /// Parses features string setting specified subtarget options. Definition of
   /// function is auto generated by tblgen.