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Merge isSHUFPMask and isCommutedSHUFPMask into single function that can do both. Do the same for the 256-bit version. Use loops to reduce size of isVSHUFPYMask. Fix test cases that were incorrectly passing due to isCommutedSHUFPMask not checking for the vector being 128-bit. This caused some 256-bit shuffles to be incorrectly commuted.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145921 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper
parent
df33e0d05e
commit
1ff73d7a67
@ -3251,7 +3251,7 @@ static bool isPALIGNRMask(const SmallVectorImpl<int> &Mask, EVT VT,
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/// specifies a shuffle of elements that is suitable for input to 256-bit
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/// VSHUFPSY.
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static bool isVSHUFPYMask(const SmallVectorImpl<int> &Mask, EVT VT,
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bool HasAVX) {
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bool HasAVX, bool Commuted = false) {
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int NumElems = VT.getVectorNumElements();
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if (!HasAVX || VT.getSizeInBits() != 256)
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@ -3279,114 +3279,27 @@ static bool isVSHUFPYMask(const SmallVectorImpl<int> &Mask, EVT VT,
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//
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// DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0
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//
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int QuarterSize = NumElems/4;
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int HalfSize = QuarterSize*2;
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for (int i = 0; i < QuarterSize; ++i)
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if (!isUndefOrInRange(Mask[i], 0, HalfSize))
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return false;
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for (int i = QuarterSize; i < QuarterSize*2; ++i)
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if (!isUndefOrInRange(Mask[i], NumElems, NumElems+HalfSize))
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return false;
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// For VSHUFPSY, the mask of the second half must be the same as the first
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// but with the appropriate offsets. This works in the same way as
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// VPERMILPS works with masks.
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for (int i = QuarterSize*2; i < QuarterSize*3; ++i) {
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if (!isUndefOrInRange(Mask[i], HalfSize, NumElems))
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return false;
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if (NumElems == 4)
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continue;
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// VSHUFPSY handling
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int FstHalfIdx = i-HalfSize;
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if (Mask[FstHalfIdx] < 0)
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continue;
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if (!isUndefOrEqual(Mask[i], Mask[FstHalfIdx]+HalfSize))
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return false;
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}
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for (int i = QuarterSize*3; i < NumElems; ++i) {
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if (!isUndefOrInRange(Mask[i], NumElems+HalfSize, NumElems*2))
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return false;
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int FstHalfIdx = i-HalfSize;
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if (NumElems == 4)
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continue;
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// VSHUFPSY handling
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if (Mask[FstHalfIdx] < 0)
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continue;
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if (!isUndefOrEqual(Mask[i], Mask[FstHalfIdx]+HalfSize))
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return false;
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}
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return true;
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}
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/// isCommutedVSHUFP() - Returns true if the shuffle mask is exactly
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/// the reverse of what x86 shuffles want. x86 shuffles requires the lower
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/// half elements to come from vector 1 (which would equal the dest.) and
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/// the upper half to come from vector 2.
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static bool isCommutedVSHUFPYMask(const SmallVectorImpl<int> &Mask, EVT VT,
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bool HasAVX) {
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int NumElems = VT.getVectorNumElements();
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if (!HasAVX || VT.getSizeInBits() != 256)
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return false;
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if (NumElems != 4 && NumElems != 8)
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return false;
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// VSHUFPSY divides the resulting vector into 4 chunks.
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// The sources are also splitted into 4 chunks, and each destination
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// chunk must come from a different source chunk.
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//
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// SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
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// SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
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//
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// DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
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// Y3..Y0, Y3..Y0, X3..X0, X3..X0
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//
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// VSHUFPDY divides the resulting vector into 4 chunks.
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// The sources are also splitted into 4 chunks, and each destination
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// chunk must come from a different source chunk.
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//
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// SRC1 => X3 X2 X1 X0
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// SRC2 => Y3 Y2 Y1 Y0
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//
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// DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0
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//
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int QuarterSize = NumElems/4;
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int HalfSize = QuarterSize*2;
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for (int i = 0; i < QuarterSize; ++i)
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if (!isUndefOrInRange(Mask[i], NumElems, NumElems+HalfSize))
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return false;
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for (int i = QuarterSize; i < QuarterSize*2; ++i)
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if (!isUndefOrInRange(Mask[i], 0, HalfSize))
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return false;
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// For VSHUFPSY, the mask of the second half must be the same as the first
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// but with the appropriate offsets. This works in the same way as
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// VPERMILPS works with masks.
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for (int i = QuarterSize*2; i < QuarterSize*3; ++i) {
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if (!isUndefOrInRange(Mask[i], NumElems+HalfSize, NumElems*2))
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return false;
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if (NumElems == 4)
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continue;
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// VSHUFPSY handling
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int FstHalfIdx = i-HalfSize;
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if (Mask[FstHalfIdx] < 0)
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continue;
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if (!isUndefOrEqual(Mask[i], Mask[FstHalfIdx]+HalfSize))
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return false;
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}
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for (int i = QuarterSize*3; i < NumElems; ++i) {
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if (!isUndefOrInRange(Mask[i], HalfSize, NumElems))
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return false;
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if (NumElems == 4)
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continue;
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// VSHUFPSY handling
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int FstHalfIdx = i-HalfSize;
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if (Mask[FstHalfIdx] < 0)
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continue;
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if (!isUndefOrEqual(Mask[i], Mask[FstHalfIdx]+HalfSize))
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return false;
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unsigned QuarterSize = NumElems/4;
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unsigned HalfSize = QuarterSize*2;
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for (unsigned l = 0; l != 2; ++l) {
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unsigned LaneStart = l*HalfSize;
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for (unsigned s = 0; s != 2; ++s) {
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unsigned QuarterStart = s*QuarterSize;
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unsigned Src = (Commuted) ? (1-s) : s;
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unsigned SrcStart = Src*NumElems + LaneStart;
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for (unsigned i = 0; i != QuarterSize; ++i) {
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int Idx = Mask[i+QuarterStart+LaneStart];
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if (!isUndefOrInRange(Idx, SrcStart, SrcStart+HalfSize))
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return false;
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// For VSHUFPSY, the mask of the second half must be the same as the first
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// but with the appropriate offsets. This works in the same way as
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// VPERMILPS works with masks.
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if (NumElems == 4 || l == 0 || Mask[i+QuarterStart] < 0)
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continue;
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if (!isUndefOrEqual(Idx, Mask[i+QuarterStart]+HalfSize))
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return false;
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}
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}
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}
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return true;
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@ -3436,9 +3349,11 @@ static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
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/// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
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/// specifies a shuffle of elements that is suitable for input to 128-bit
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/// SHUFPS and SHUFPD.
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static bool isSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) {
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int NumElems = VT.getVectorNumElements();
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/// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be
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/// reverse of what x86 shuffles want.
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static bool isSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT,
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bool Commuted = false) {
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unsigned NumElems = VT.getVectorNumElements();
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if (VT.getSizeInBits() != 128)
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return false;
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@ -3446,12 +3361,14 @@ static bool isSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) {
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if (NumElems != 2 && NumElems != 4)
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return false;
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int Half = NumElems / 2;
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for (int i = 0; i < Half; ++i)
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if (!isUndefOrInRange(Mask[i], 0, NumElems))
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unsigned Half = NumElems / 2;
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unsigned SrcStart = Commuted ? NumElems : 0;
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for (unsigned i = 0; i != Half; ++i)
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if (!isUndefOrInRange(Mask[i], SrcStart, SrcStart+NumElems))
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return false;
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for (int i = Half; i < NumElems; ++i)
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if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2))
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SrcStart = Commuted ? 0 : NumElems;
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for (unsigned i = Half; i != NumElems; ++i)
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if (!isUndefOrInRange(Mask[i], SrcStart, SrcStart+NumElems))
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return false;
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return true;
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@ -3463,26 +3380,6 @@ bool X86::isSHUFPMask(ShuffleVectorSDNode *N) {
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return ::isSHUFPMask(M, N->getValueType(0));
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}
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/// isCommutedSHUFPMask - Returns true if the shuffle mask is exactly
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/// the reverse of what x86 shuffles want. x86 shuffles requires the lower
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/// half elements to come from vector 1 (which would equal the dest.) and
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/// the upper half to come from vector 2.
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static bool isCommutedSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) {
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int NumElems = VT.getVectorNumElements();
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if (NumElems != 2 && NumElems != 4)
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return false;
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int Half = NumElems / 2;
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for (int i = 0; i < Half; ++i)
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if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2))
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return false;
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for (int i = Half; i < NumElems; ++i)
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if (!isUndefOrInRange(Mask[i], 0, NumElems))
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return false;
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return true;
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}
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/// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
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/// specifies a shuffle of elements that is suitable for input to MOVHLPS.
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bool X86::isMOVHLPSMask(ShuffleVectorSDNode *N) {
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@ -6780,8 +6677,8 @@ X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
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}
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// Normalize the node to match x86 shuffle ops if needed
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if (!V2IsUndef && (isCommutedSHUFPMask(M, VT) ||
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isCommutedVSHUFPYMask(M, VT, HasAVX)))
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if (!V2IsUndef && (isSHUFPMask(M, VT, /* Commuted */ true) ||
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isVSHUFPYMask(M, VT, HasAVX, /* Commuted */ true)))
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return CommuteVectorShuffle(SVOp, DAG);
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// The checks below are all present in isShuffleMaskLegal, but they are
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@ -11272,7 +11169,7 @@ X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
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return (isMOVLMask(Mask, VT) ||
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isCommutedMOVLMask(Mask, VT, true) ||
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isSHUFPMask(Mask, VT) ||
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isCommutedSHUFPMask(Mask, VT));
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isSHUFPMask(Mask, VT, /* Commuted */ true));
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}
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return false;
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}
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@ -1,5 +1,6 @@
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; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -mattr=+avx | FileCheck %s
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; CHECK: _A
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; CHECK: vperm2f128 $1
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define <8 x float> @A(<8 x float> %a, <8 x float> %b) nounwind uwtable readnone ssp {
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entry:
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@ -7,6 +8,7 @@ entry:
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ret <8 x float> %shuffle
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}
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; CHECK: _B
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; CHECK: vperm2f128 $48
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define <8 x float> @B(<8 x float> %a, <8 x float> %b) nounwind uwtable readnone ssp {
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entry:
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@ -14,6 +16,7 @@ entry:
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ret <8 x float> %shuffle
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}
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; CHECK: _C
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; CHECK: vperm2f128 $0
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define <8 x float> @C(<8 x float> %a, <8 x float> %b) nounwind uwtable readnone ssp {
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entry:
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@ -21,6 +24,7 @@ entry:
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ret <8 x float> %shuffle
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}
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; CHECK: _D
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; CHECK: vperm2f128 $17
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define <8 x float> @D(<8 x float> %a, <8 x float> %b) nounwind uwtable readnone ssp {
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entry:
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@ -28,6 +32,7 @@ entry:
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ret <8 x float> %shuffle
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}
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; CHECK: _E
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; CHECK: vperm2f128 $17
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define <32 x i8> @E(<32 x i8> %a, <32 x i8> %b) nounwind uwtable readnone ssp {
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entry:
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@ -35,7 +40,8 @@ entry:
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ret <32 x i8> %shuffle
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}
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; CHECK: vperm2f128 $33
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; CHECK: _E2
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; CHECK: vperm2f128 $3
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define <4 x i64> @E2(<4 x i64> %a, <4 x i64> %b) nounwind uwtable readnone ssp {
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entry:
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%shuffle = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> <i32 6, i32 7, i32 0, i32 1>
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@ -44,6 +50,7 @@ entry:
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;;;; Cases with undef indicies mixed in the mask
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; CHECK: _F
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; CHECK: vperm2f128 $33
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define <8 x float> @F(<8 x float> %a, <8 x float> %b) nounwind uwtable readnone ssp {
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entry:
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@ -9,7 +9,7 @@ entry:
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ret <32 x i8> %shuffle
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}
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; CHECK: vperm2i128 $33
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; CHECK: vperm2i128 $3
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define <4 x i64> @E2(<4 x i64> %a, <4 x i64> %b) nounwind uwtable readnone ssp {
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entry:
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; add forces execution domain
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