Detabification. Fixed indentation and spacing.

Changed cout to DOUT, and TODOs to FIXMEs.
Other changes as per coding conventions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51105 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/PIC16/PIC16AsmPrinter.cpp

@@ -117,7 +117,7 @@ FunctionPass *llvm::createPIC16CodePrinterPass(std::ostream &o,
 
 void PIC16AsmPrinter::getAnalysisUsage(AnalysisUsage &AU) const 
 {
-  // Currently unimplemented.
+  // FIXME: Currently unimplemented.
 }
 
 
@@ -137,8 +137,10 @@ EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV)
   } else if (ACPV->isStub()) {
     FnStubs.insert(Name);
     O << TAI->getPrivateGlobalPrefix() << Name << "$stub";
-  } else
+  } else {
     O << Name;
+  }
+
   if (ACPV->hasModifier()) O << "(" << ACPV->getModifier() << ")";
 
   if (ACPV->getPCAdjustment() != 0) {
@@ -159,8 +161,9 @@ EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV)
     ExtWeakSymbols.insert(GV);
 }
 
-/// Emit the directives used by ASM on the start of functions
+/// emitFunctionStart - Emit the directives used by ASM on the start of 
-void PIC16AsmPrinter:: emitFunctionStart(MachineFunction &MF)
+/// functions.
+void PIC16AsmPrinter::emitFunctionStart(MachineFunction &MF)
 {
   // Print out the label for the function.
   const Function *F = MF.getFunction();
@@ -168,8 +171,8 @@ void PIC16AsmPrinter:: emitFunctionStart(MachineFunction &MF)
   if (FrameInfo->hasStackObjects()) {           
     int indexBegin = FrameInfo->getObjectIndexBegin();
     int indexEnd = FrameInfo->getObjectIndexEnd();
-     while (indexBegin<indexEnd) {
+    while (indexBegin < indexEnd) {
-       if (indexBegin ==0)                     
+      if (indexBegin == 0)                     
         SwitchToDataOvrSection(F->getParent()->getModuleIdentifier().c_str(),
                                 F);
                  
@@ -187,27 +190,17 @@ void PIC16AsmPrinter:: emitFunctionStart(MachineFunction &MF)
 /// runOnMachineFunction - This uses the printInstruction()
 /// method to print assembly for each instruction.
 ///
-bool PIC16AsmPrinter::
+bool PIC16AsmPrinter::runOnMachineFunction(MachineFunction &MF) 
-runOnMachineFunction(MachineFunction &MF) 
 {
-
-  // DW.SetModuleInfo(&getAnalysis<MachineModuleInfo>());
   SetupMachineFunction(MF);
   O << "\n";
 
-  // NOTE: we don't print out constant pools here, they are handled as
-  // instructions.
-  O << "\n";
-
   // What's my mangled name?
   CurrentFnName = Mang->getValueName(MF.getFunction());
 
   // Emit the function start directives
   emitFunctionStart(MF);
 
-  // Emit pre-function debug information.
-  // DW.BeginFunction(&MF);
-
   // Print out code for the function.
   for (MachineFunction::const_iterator I = MF.begin(), E = MF.end();
        I != E; ++I) {
@@ -225,9 +218,6 @@ runOnMachineFunction(MachineFunction &MF)
     }
   }
 
-  // Emit post-function debug information.
-  // DW.EndFunction();
-
   // We didn't modify anything.
   return false;
 }
@@ -238,61 +228,50 @@ printOperand(const MachineInstr *MI, int opNum, const char *Modifier)
   const MachineOperand &MO = MI->getOperand(opNum);
   const TargetRegisterInfo  &RI = *TM.getRegisterInfo();
 
-  switch (MO.getType()) 
+  switch (MO.getType()) {
-  {
     case MachineOperand::MO_Register:
-    {
       if (TargetRegisterInfo::isPhysicalRegister(MO.getReg()))
         O << RI.get(MO.getReg()).Name;
       else
         assert(0 && "not implemented");
       break;
-    }
+
     case MachineOperand::MO_Immediate: 
-    {
       if (!Modifier || strcmp(Modifier, "no_hash") != 0)
         O << "#";
       O << (int)MO.getImm();
       break;
-    }
+
     case MachineOperand::MO_MachineBasicBlock:
-    {
       printBasicBlockLabel(MO.getMBB());
       return;
-    }
+
     case MachineOperand::MO_GlobalAddress: 
-    {
       O << Mang->getValueName(MO.getGlobal())<<'+'<<MO.getOffset();
       break;
-    }
+
     case MachineOperand::MO_ExternalSymbol: 
-    {
       O << MO.getSymbolName();
       break;
-    }
+
     case MachineOperand::MO_ConstantPoolIndex:
-    {
       O << TAI->getPrivateGlobalPrefix() << "CPI" << getFunctionNumber()
         << '_' << MO.getIndex();
       break;
-    }
+
     case MachineOperand::MO_FrameIndex:
-    {
       O << "_" << CurrentFnName 
         << '+' << MO.getIndex();
       break;
-    }
+
     case MachineOperand::MO_JumpTableIndex:
-    {
       O << TAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber()
         << '_' << MO.getIndex();
       break;
-    }
+
     default:
-    {
       O << "<unknown operand type>"; abort (); 
       break;
-    }
   } // end switch.
 }
 
@@ -300,15 +279,13 @@ static void
 printSOImm(std::ostream &O, int64_t V, const TargetAsmInfo *TAI) 
 {
   assert(V < (1 << 12) && "Not a valid so_imm value!");
-  unsigned Imm = V;
   
-  O << Imm;
+  O << (unsigned) V;
 }
 
-/// printSOImmOperand - SOImm is 4-bit rotate amount in bits 8-11 with 8-bit
+/// printSOImmOperand - SOImm is 4-bit rotated amount in bits 8-11 with 8-bit
 /// immediate in bits 0-7.
-void PIC16AsmPrinter::
+void PIC16AsmPrinter::printSOImmOperand(const MachineInstr *MI, int OpNum) 
-printSOImmOperand(const MachineInstr *MI, int OpNum) 
 {
   const MachineOperand &MO = MI->getOperand(OpNum);
   assert(MO.isImmediate() && "Not a valid so_imm value!");
@@ -316,7 +293,7 @@ printSOImmOperand(const MachineInstr *MI, int OpNum)
 }
 
 
-void PIC16AsmPrinter:: printAddrModeOperand(const MachineInstr *MI, int Op) 
+void PIC16AsmPrinter::printAddrModeOperand(const MachineInstr *MI, int Op) 
 {
   const MachineOperand &MO1 = MI->getOperand(Op);
   const MachineOperand &MO2 = MI->getOperand(Op+1);
@@ -326,15 +303,15 @@ void PIC16AsmPrinter:: printAddrModeOperand(const MachineInstr *MI, int Op)
     return;
   }
 
-  if (!MO1.isRegister()) {   // FIXME: This is for CP entries, but isn't right.
+  if (!MO1.isRegister()) {   
+    // FIXME: This is for CP entries, but isn't right.
     printOperand(MI, Op);
     return;
   }
 
   // If this is Stack Slot
   if (MO1.isRegister()) {  
-    if(strcmp(TM.getRegisterInfo()->get(MO1.getReg()).Name, "SP")==0) 
+    if (strcmp(TM.getRegisterInfo()->get(MO1.getReg()).Name, "SP") == 0) {
-    {
       O << CurrentFnName <<"_"<< MO2.getImm();
       return;
     }
@@ -350,7 +327,7 @@ void PIC16AsmPrinter:: printAddrModeOperand(const MachineInstr *MI, int Op)
 }
 
 
-void PIC16AsmPrinter:: printRegisterList(const MachineInstr *MI, int opNum) 
+void PIC16AsmPrinter::printRegisterList(const MachineInstr *MI, int opNum) 
 {
   O << "{";
   for (unsigned i = opNum, e = MI->getNumOperands(); i != e; ++i) {
@@ -391,16 +368,13 @@ printCPInstOperand(const MachineInstr *MI, int OpNo, const char *Modifier)
 }
 
 
-bool PIC16AsmPrinter:: doInitialization(Module &M) 
+bool PIC16AsmPrinter::doInitialization(Module &M) 
 {
-  // Emit initial debug information.
-  // DW.BeginModule(&M);
-
   bool Result = AsmPrinter::doInitialization(M);
   return Result;
 }
 
-bool PIC16AsmPrinter:: doFinalization(Module &M) 
+bool PIC16AsmPrinter::doFinalization(Module &M) 
 {
   const TargetData *TD = TM.getTargetData();
 
@@ -415,8 +389,8 @@ bool PIC16AsmPrinter:: doFinalization(Module &M)
 
     std::string name = Mang->getValueName(I);
     Constant *C = I->getInitializer();
-    const Type *Type = C->getType();
+    const Type *Ty = C->getType();
-    unsigned Size = TD->getABITypeSize(Type);
+    unsigned Size = TD->getABITypeSize(Ty);
     unsigned Align = TD->getPreferredAlignmentLog(I);
 
     const char *VisibilityDirective = NULL;
@@ -465,21 +439,17 @@ bool PIC16AsmPrinter:: doFinalization(Module &M)
       }
     }
 
-    switch (I->getLinkage()) 
+    switch (I->getLinkage()) {
-    {
     case GlobalValue::AppendingLinkage:
-    {
       // FIXME: appending linkage variables should go into a section of
       // their name or something.  For now, just emit them as external.
-      // Fall through
+      // FALL THROUGH
-    }
+
     case GlobalValue::ExternalLinkage:
-    {
       O << "\t.globl " << name << "\n";
       // FALL THROUGH
-    }
+
     case GlobalValue::InternalLinkage: 
-    {
       if (I->isConstant()) {
         const ConstantArray *CVA = dyn_cast<ConstantArray>(C);
         if (TAI->getCStringSection() && CVA && CVA->isCString()) {
@@ -488,12 +458,10 @@ bool PIC16AsmPrinter:: doFinalization(Module &M)
         }
       }
       break;
-    }
+
     default:
-    {
       assert(0 && "Unknown linkage type!");
       break;
-    }
     } // end switch.
 
     EmitAlignment(Align, I);
@@ -523,29 +491,29 @@ SwitchToTextSection(const char *NewSection, const GlobalValue *GV)
     codeSection += NewSection;
     codeSection += " ";
     codeSection += "CODE";
-     AsmPrinter::SwitchToTextSection(codeSection.c_str(),GV);
+    AsmPrinter::SwitchToTextSection(codeSection.c_str(), GV);
   } 
   else 
-     AsmPrinter::SwitchToTextSection(NewSection,GV);
+    AsmPrinter::SwitchToTextSection(NewSection, GV);
 }
 
 void PIC16AsmPrinter::
 SwitchToDataSection(const char *NewSection, const GlobalValue *GV)
 {
-   //Need to append index for page
+  // Need to append index for page.
   O << "\n";
   if (NewSection && *NewSection) {
-     std::string dataSection ="udata_";
+    std::string dataSection = "udata_";
-     dataSection+=NewSection;
+    dataSection += NewSection;
-     if (dataSection.substr(dataSection.length()-2).compare(".o") == 0) {
+    if (dataSection.substr(dataSection.length() - 2).compare(".o") == 0) {
-        dataSection = dataSection.substr(0,dataSection.length()-2);
+      dataSection = dataSection.substr(0, dataSection.length() - 2);
     }
     dataSection += " ";
     dataSection += "UDATA";
-     AsmPrinter::SwitchToDataSection(dataSection.c_str(),GV);
+    AsmPrinter::SwitchToDataSection(dataSection.c_str(), GV);
   } 
   else
-     AsmPrinter::SwitchToDataSection(NewSection,GV);
+    AsmPrinter::SwitchToDataSection(NewSection, GV);
 }
 
 void PIC16AsmPrinter::
@@ -555,15 +523,15 @@ SwitchToDataOvrSection(const char *NewSection, const GlobalValue *GV)
   if (NewSection && *NewSection) {
     std::string dataSection = "frame_";
     dataSection += NewSection;
-      if (dataSection.substr(dataSection.length()-2).compare(".o") == 0) {
+    if (dataSection.substr(dataSection.length() - 2).compare(".o") == 0) {
-         dataSection = dataSection.substr(0,dataSection.length()-2);
+      dataSection = dataSection.substr(0, dataSection.length() - 2);
     }          
     dataSection += "_";
     dataSection += CurrentFnName;
     dataSection += " ";
     dataSection += "UDATA_OVR";
-      AsmPrinter::SwitchToDataSection(dataSection.c_str(),GV);
+    AsmPrinter::SwitchToDataSection(dataSection.c_str(), GV);
   } 
   else
-      AsmPrinter::SwitchToDataSection(NewSection,GV);
+    AsmPrinter::SwitchToDataSection(NewSection, GV);
 }

lib/Target/PIC16/PIC16CallingConv.td

@@ -1,4 +1,4 @@
-//===- PIC16CallingConv.td - Calling Conventions Sparc -----*- tablegen -*-===//
+//===- PIC16CallingConv.td - Calling Conventions PIC16 -----*- tablegen -*-===//
 // 
 //                     The LLVM Compiler Infrastructure
 //
@@ -14,4 +14,3 @@
 //===----------------------------------------------------------------------===//
 // Return Value Calling Conventions
 //===----------------------------------------------------------------------===//
-

lib/Target/PIC16/PIC16ISelDAGToDAG.cpp

@@ -56,11 +56,6 @@ class VISIBILITY_HIDDEN PIC16DAGToDAGISel : public SelectionDAGISel {
   /// PIC16-specific SelectionDAG.
   PIC16TargetLowering PIC16Lowering;
 
-  /// Subtarget - Keep a pointer to the PIC16Subtarget around so that we can
-  /// make the right decision when generating code for different targets.
-  //TODO: add initialization on constructor
-  //const PIC16Subtarget *Subtarget;
- 
 public:
   PIC16DAGToDAGISel(PIC16TargetMachine &tm) : 
         SelectionDAGISel(PIC16Lowering),
@@ -75,7 +70,7 @@ public:
   
 private:
   // Include the pieces autogenerated from the target description.
-  #include "PIC16GenDAGISel.inc"
+#include "PIC16GenDAGISel.inc"
 
   SDNode *Select(SDOperand N);
 
@@ -95,9 +90,9 @@ private:
   }
 
 
-  #ifndef NDEBUG
+#ifndef NDEBUG
   unsigned Indent;
-  #endif
+#endif
 };
 
 }
@@ -108,17 +103,16 @@ void PIC16DAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &SD)
 {
   DEBUG(BB->dump());
   // Codegen the basic block.
-  #ifndef NDEBUG
+
   DOUT << "===== Instruction selection begins:\n";
+#ifndef NDEBUG
   Indent = 0;
-  #endif
+#endif
 
   // Select target instructions for the DAG.
   SD.setRoot(SelectRoot(SD.getRoot()));
 
-  #ifndef NDEBUG
   DOUT << "===== Instruction selection ends:\n";
-  #endif
 
   SD.RemoveDeadNodes();
   
@@ -135,7 +129,7 @@ SelectDirectAM (SDOperand Op, SDOperand N, SDOperand &Base, SDOperand &Offset)
 
   // if Address is FI, get the TargetFrameIndex.
   if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(N)) {
-    cout << "--------- its frame Index\n";
+    DOUT << "--------- its frame Index\n";
     Base   = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
     Offset = CurDAG->getTargetConstant(0, MVT::i32);
     return true;
@@ -168,7 +162,7 @@ SelectDirectAM (SDOperand Op, SDOperand N, SDOperand &Base, SDOperand &Offset)
 }
 
 
-//FIXME: must also account for preinc/predec/postinc/postdec
+// FIXME: must also account for preinc/predec/postinc/postdec.
 bool PIC16DAGToDAGISel::
 StoreInDirectAM (SDOperand Op, SDOperand N, SDOperand &fsr)
 {
@@ -181,12 +175,12 @@ StoreInDirectAM (SDOperand Op, SDOperand N, SDOperand &fsr)
     else if (isa<RegisterSDNode>(N.Val)) { 
       //FIXME an attempt to retrieve the register number
       //but does not work
-      cout << "this is a register\n";
+      DOUT << "this is a register\n";
       Reg = dyn_cast<RegisterSDNode>(N.Val);
       fsr = CurDAG->getRegister(Reg->getReg(),MVT::i16);  
     }
     else {
-      cout << "this is not a register\n";
+      DOUT << "this is not a register\n";
       // FIXME must use whatever load is using
       fsr = CurDAG->getRegister(1,MVT::i16);
     }
@@ -215,14 +209,14 @@ LoadFSR (SDOperand Op, SDOperand N, SDOperand &Base, SDOperand &Offset)
   return false;
 }
 
-//don't thake this seriously, it will change
+// LoadNothing - Don't thake this seriously, it will change.
 bool PIC16DAGToDAGISel::
 LoadNothing (SDOperand Op, SDOperand N, SDOperand &Base, SDOperand &Offset)
 {
   GlobalAddressSDNode *GA;
   if (N.getOpcode() == ISD::GlobalAddress) {
     GA = dyn_cast<GlobalAddressSDNode>(N);
-    cout << "==========" << GA->getOffset() << "\n";
+    DOUT << "==========" << GA->getOffset() << "\n";
     Offset = CurDAG->getTargetConstant((unsigned char)GA->getOffset(), MVT::i8);
     Base = CurDAG->getTargetGlobalAddress(GA->getGlobal(), MVT::i16,
                                           GA->getOffset());
@@ -233,34 +227,34 @@ LoadNothing (SDOperand Op, SDOperand N, SDOperand &Base, SDOperand &Offset)
 }
 
 
-/// Select instructions not customized! Used for
+/// Select - Select instructions not customized! Used for
-/// expanded, promoted and normal instructions
+/// expanded, promoted and normal instructions.
 SDNode* PIC16DAGToDAGISel::Select(SDOperand N) 
 {
   SDNode *Node = N.Val;
   unsigned Opcode = Node->getOpcode();
 
   // Dump information about the Node being selected
-  #ifndef NDEBUG
+#ifndef NDEBUG
   DOUT << std::string(Indent, ' ') << "Selecting: ";
   DEBUG(Node->dump(CurDAG));
   DOUT << "\n";
   Indent += 2;
-  #endif
+#endif
 
   // If we have a custom node, we already have selected!
   if (Opcode >= ISD::BUILTIN_OP_END && Opcode < PIC16ISD::FIRST_NUMBER) {
-    #ifndef NDEBUG
+#ifndef NDEBUG
     DOUT << std::string(Indent-2, ' ') << "== ";
     DEBUG(Node->dump(CurDAG));
     DOUT << "\n";
     Indent -= 2;
-    #endif
+#endif
     return NULL;
   }
 
   ///
-  // Instruction Selection not handled by custom or by the 
+  // FIXME: Instruction Selection not handled by custom or by the 
   // auto-generated tablegen selection should be handled here.
   /// 
   switch(Opcode) {
@@ -270,7 +264,7 @@ SDNode* PIC16DAGToDAGISel::Select(SDOperand N)
   // Select the default instruction.
   SDNode *ResNode = SelectCode(N);
 
-  #ifndef NDEBUG
+#ifndef NDEBUG
   DOUT << std::string(Indent-2, ' ') << "=> ";
   if (ResNode == NULL || ResNode == N.Val)
     DEBUG(N.Val->dump(CurDAG));
@@ -278,7 +272,7 @@ SDNode* PIC16DAGToDAGISel::Select(SDOperand N)
     DEBUG(ResNode->dump(CurDAG));
   DOUT << "\n";
   Indent -= 2;
-  #endif
+#endif
 
   return ResNode;
 }

lib/Target/PIC16/PIC16ISelLowering.cpp

@@ -35,8 +35,7 @@ using namespace llvm;
 
 const char *PIC16TargetLowering:: getTargetNodeName(unsigned Opcode) const 
 {
-  switch (Opcode) 
+  switch (Opcode) {
-  {
     case PIC16ISD::Hi        : return "PIC16ISD::Hi";
     case PIC16ISD::Lo        : return "PIC16ISD::Lo";
     case PIC16ISD::Package   : return "PIC16ISD::Package";
@@ -56,30 +55,15 @@ const char *PIC16TargetLowering:: getTargetNodeName(unsigned Opcode) const
 PIC16TargetLowering::
 PIC16TargetLowering(PIC16TargetMachine &TM): TargetLowering(TM) 
 {
-  // PIC16 does not have i1 type, so use i8 for
+  // Set up the register classes.
-  // setcc operations results (slt, sgt, ...). 
-  // setSetCCResultType(MVT::i8);
-  // setSetCCResultContents(ZeroOrOneSetCCResult);
-
-  // Set up the register classes
   addRegisterClass(MVT::i8, PIC16::CPURegsRegisterClass);
   addRegisterClass(MVT::i16, PIC16::PTRRegsRegisterClass);
-  // Custom
 
-  // Load extented operations for i1 types must be promoted 
+  // Load extented operations for i1 types must be promoted .
   setLoadXAction(ISD::EXTLOAD, MVT::i1,  Promote);
   setLoadXAction(ISD::ZEXTLOAD, MVT::i1,  Promote);
   setLoadXAction(ISD::SEXTLOAD, MVT::i1,  Promote);
 
-  // Store operations for i1 types must be promoted
-  // setStoreXAction(MVT::i1, Promote);
-  // setStoreXAction(MVT::i8, Legal);
-  // setStoreXAction(MVT::i16, Custom);
-  // setStoreXAction(MVT::i32, Expand);
-
-  // setOperationAction(ISD::BUILD_PAIR,     MVT::i32,  Expand);
-  // setOperationAction(ISD::BUILD_PAIR,     MVT::i16,  Expand);
-
   setOperationAction(ISD::ADD, MVT::i1, Promote);
   setOperationAction(ISD::ADD, MVT::i8, Legal);
   setOperationAction(ISD::ADD, MVT::i16, Custom);
@@ -126,27 +110,22 @@ PIC16TargetLowering(PIC16TargetMachine &TM): TargetLowering(TM)
   setOperationAction(ISD::BRCOND, MVT::i1, Expand);
   setOperationAction(ISD::BRCOND, MVT::i8, Expand);
   setOperationAction(ISD::BRCOND, MVT::Other, Expand);
+
   setOperationAction(ISD::BR_CC, MVT::i1, Custom);
   setOperationAction(ISD::BR_CC, MVT::i8, Custom);
 
   setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
 
   
-  // Do we really need to Custom lower the GA ??
+  // FIXME: Do we really need to Custom lower the GA ??
-  // setOperationAction(ISD::GlobalAddress, MVT::i16, Custom);
   setOperationAction(ISD::GlobalAddress, MVT::i8, Custom);
   setOperationAction(ISD::RET, MVT::Other, Custom);
 
-  // PIC16 not supported intrinsics.
-  // setOperationAction(ISD::MEMMOVE, MVT::Other, Expand);
-  // setOperationAction(ISD::MEMSET, MVT::Other, Expand);
-  // setOperationAction(ISD::MEMCPY, MVT::Other, Expand);
-
   setOperationAction(ISD::CTPOP, MVT::i32, Expand);
-  setOperationAction(ISD::CTTZ , MVT::i32, Expand);
+  setOperationAction(ISD::CTTZ, MVT::i32, Expand);
-  setOperationAction(ISD::CTLZ , MVT::i32, Expand);
+  setOperationAction(ISD::CTLZ, MVT::i32, Expand);
-  setOperationAction(ISD::ROTL , MVT::i32, Expand);
+  setOperationAction(ISD::ROTL, MVT::i32, Expand);
-  setOperationAction(ISD::ROTR , MVT::i32, Expand);
+  setOperationAction(ISD::ROTR, MVT::i32, Expand);
   setOperationAction(ISD::BSWAP, MVT::i32, Expand);
 
   setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
@@ -158,14 +137,12 @@ PIC16TargetLowering(PIC16TargetMachine &TM): TargetLowering(TM)
   setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
   setOperationAction(ISD::LABEL, MVT::Other, Expand);
 
-  // Use the default for now
+  // Use the default for now.
   setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
   setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
 
   setOperationAction(ISD::LOAD, MVT::i1, Promote);
   setOperationAction(ISD::LOAD, MVT::i8, Legal);
-  // setOperationAction(ISD::LOAD, MVT::i16, Expand);
-  // setOperationAction(ISD::LOAD, MVT::i32, Expand);
 
   setTargetDAGCombine(ISD::LOAD);
   setTargetDAGCombine(ISD::STORE);
@@ -176,11 +153,6 @@ PIC16TargetLowering(PIC16TargetMachine &TM): TargetLowering(TM)
   setTargetDAGCombine(ISD::SUBC);
   setTargetDAGCombine(ISD::SUB);
 
-  // We must find a way to get rid of Package nodes in the map
-  // setTargetDAGCombine(PIC16ISD::Package);
-
-  // getValueTypeActions().setTypeAction((MVT::ValueType)MVT::i16, Expand);
-
   setStackPointerRegisterToSaveRestore(PIC16::STKPTR);
   computeRegisterProperties();
 }
@@ -189,33 +161,39 @@ PIC16TargetLowering(PIC16TargetMachine &TM): TargetLowering(TM)
 SDOperand PIC16TargetLowering:: LowerOperation(SDOperand Op, SelectionDAG &DAG) 
 {
   SDVTList VTList16 = DAG.getVTList(MVT::i16, MVT::i16, MVT::Other);
-  switch (Op.getOpcode()) 
+  switch (Op.getOpcode()) {
-  {
     case ISD::STORE: 
-      cout << "reduce store\n"; 
+      DOUT << "reduce store\n"; 
       break;
+
     case ISD::FORMAL_ARGUMENTS:   
-      cout<<"==== lowering formal args\n";
+      DOUT << "==== lowering formal args\n";
       return LowerFORMAL_ARGUMENTS(Op, DAG);
+
     case ISD::GlobalAddress:      
-      cout<<"==== lowering GA\n";
+      DOUT << "==== lowering GA\n";
       return LowerGlobalAddress(Op, DAG);
+
     case ISD::RET:                
-      cout<<"==== lowering ret\n";
+      DOUT << "==== lowering ret\n";
       return LowerRET(Op, DAG);
+
     case ISD::FrameIndex:                
-      cout<<"==== lowering frame index\n";
+      DOUT << "==== lowering frame index\n";
       return LowerFrameIndex(Op, DAG);
+
     case ISD::ADDE: 
-      cout <<"==== lowering adde\n"; 
+      DOUT << "==== lowering adde\n"; 
       break;
+
     case ISD::LOAD:
     case ISD::ADD: 
       break;
+
     case ISD::BR_CC:                
-      cout << "==== lowering BR_CC\n"; 
+      DOUT << "==== lowering BR_CC\n"; 
       return LowerBR_CC(Op, DAG); 
-  } //end swithch
+  } // end switch.
   return SDOperand();
 }
 
@@ -224,9 +202,7 @@ SDOperand PIC16TargetLowering:: LowerOperation(SDOperand Op, SelectionDAG &DAG)
 //  Lower helper functions
 //===----------------------------------------------------------------------===//
 
-
+SDOperand PIC16TargetLowering::LowerBR_CC(SDOperand Op, SelectionDAG &DAG) 
-SDOperand 
-PIC16TargetLowering::LowerBR_CC(SDOperand Op, SelectionDAG &DAG) 
 {
   MVT::ValueType VT = Op.getValueType();
   SDOperand Chain = Op.getOperand(0);
@@ -239,74 +215,66 @@ PIC16TargetLowering::LowerBR_CC(SDOperand Op, SelectionDAG &DAG)
   unsigned  branchOpcode;
   SDOperand branchOperand;
 
-  SDOperand StatusReg = DAG.getRegister(PIC16::STATUSREG,MVT::i8);
+  SDOperand StatusReg = DAG.getRegister(PIC16::STATUSREG, MVT::i8);
-  SDOperand CPUReg = DAG.getRegister(PIC16::WREG,MVT::i8);
+  SDOperand CPUReg = DAG.getRegister(PIC16::WREG, MVT::i8);
-  switch(CC) 
+  switch(CC) {
-  {
     default:
       assert(0 && "This condition code is not handled yet!!");
       abort();
+
     case ISD::SETNE:
-    {
+      DOUT << "setne\n";
-      cout << "setne\n";
       cmpOpcode = PIC16ISD::XORCC;
       branchOpcode = PIC16ISD::BTFSS;
-      branchOperand = DAG.getConstant(2,MVT::i8);
+      branchOperand = DAG.getConstant(2, MVT::i8);
       break;
-    }
+
     case ISD::SETEQ:
-    {
+      DOUT << "seteq\n";
-      cout << "seteq\n";
       cmpOpcode = PIC16ISD::XORCC;
       branchOpcode = PIC16ISD::BTFSC;
-      branchOperand = DAG.getConstant(2,MVT::i8);
+      branchOperand = DAG.getConstant(2, MVT::i8);
       break;
-    }
+
     case ISD::SETGT:
-    {
       assert(0 && "Greater Than condition code is not handled yet!!");
       abort();
-    }
+      break;
+
     case ISD::SETGE:
-    {
+      DOUT << "setge\n";
-      cout << "setge\n";
       cmpOpcode = PIC16ISD::SUBCC;
       branchOpcode = PIC16ISD::BTFSS;
       branchOperand = DAG.getConstant(1, MVT::i8);
       break;
-    }
+
     case ISD::SETLT:
-    {
+      DOUT << "setlt\n";
-      cout << "setlt\n";
       cmpOpcode = PIC16ISD::SUBCC;
       branchOpcode = PIC16ISD::BTFSC;
       branchOperand = DAG.getConstant(1,MVT::i8);
       break;
-    }
+
     case ISD::SETLE:
-    {
       assert(0 && "Less Than Equal condition code is not handled yet!!");
       abort();
-    }
+      break;
   }  // End of Switch
 
    SDVTList VTList = DAG.getVTList(MVT::i8, MVT::Flag);
    SDOperand CmpValue = DAG.getNode(cmpOpcode, VTList, LHS, RHS).getValue(1);
-   // SDOperand CCOper = DAG.getConstant(CC,MVT::i8);
-   // Result = DAG.getNode(branchOpcode,VT, Chain, JumpVal, CCOper, StatusReg, 
-   //			   CmpValue);
    Result = DAG.getNode(branchOpcode, VT, Chain, JumpVal, branchOperand, 
                         StatusReg, CmpValue);
    return Result;
-	
-  // return SDOperand();
 }
 
 
 //===----------------------------------------------------------------------===//
 //  Misc Lower Operation implementation
 //===----------------------------------------------------------------------===//
-// Create a constant pool entry for global value and wrap it in a wrapper node.
+
+// LowerGlobalAddress - Create a constant pool entry for global value 
+// and wrap it in a wrapper node.
 SDOperand
 PIC16TargetLowering::LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG) 
 {
@@ -314,7 +282,7 @@ PIC16TargetLowering::LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG)
   GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
   GlobalValue *GV = GSDN->getGlobal();
 
-  //for now only do the ram.
+  // FIXME: for now only do the ram.
   SDOperand CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 2);
   SDOperand CPBank = DAG.getNode(PIC16ISD::SetBank, MVT::i8, CPAddr);
   CPAddr = DAG.getNode(PIC16ISD::Wrapper, MVT::i8, CPAddr,CPBank);
@@ -325,11 +293,11 @@ PIC16TargetLowering::LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG)
 SDOperand
 PIC16TargetLowering::LowerRET(SDOperand Op, SelectionDAG &DAG) 
 {
-  switch(Op.getNumOperands()) 
+  switch(Op.getNumOperands()) {
-  {
     default:
       assert(0 && "Do not know how to return this many arguments!");
       abort();
+
     case 1:
       return SDOperand(); // ret void is legal
   }
@@ -360,8 +328,8 @@ PIC16TargetLowering::LowerLOAD(SDNode *N,
 
   // If this load is directly stored, replace the load value with the stored
   // value.
-  // TODO: Handle store large -> read small portion.
+  // FIXME: Handle store large -> read small portion.
-  // TODO: Handle TRUNCSTORE/LOADEXT
+  // FIXME: Handle TRUNCSTORE/LOADEXT
   LoadSDNode *LD  = cast<LoadSDNode>(N);
   SDOperand Ptr   = LD->getBasePtr();
   if (LD->getExtensionType() == ISD::NON_EXTLOAD) {
@@ -381,7 +349,7 @@ PIC16TargetLowering::LowerLOAD(SDNode *N,
   toWorklist = DAG.getNode(ISD::ADD, MVT::i16, Src,
                            DAG.getConstant(1, MVT::i16));
   Outs[1] = DAG.getLoad(MVT::i8, Chain, toWorklist, NULL, 0);
-  // Add to worklist may not be needed. 
+  // FIXME: Add to worklist may not be needed. 
   // It is meant to merge sequences of add with constant into one. 
   DCI.AddToWorklist(toWorklist.Val);   
   
@@ -405,7 +373,7 @@ PIC16TargetLowering::LowerADDSUB(SDNode *N, SelectionDAG &DAG,
   bool changed = false;
   int i;
   SDOperand LoOps[3], HiOps[3];
-  SDOperand OutOps[3]; //[0]:left, [1]:right, [2]:carry
+  SDOperand OutOps[3]; // [0]:left, [1]:right, [2]:carry
   SDOperand InOp[2];
   SDOperand retVal;
   SDOperand as1,as2;
@@ -415,8 +383,7 @@ PIC16TargetLowering::LowerADDSUB(SDNode *N, SelectionDAG &DAG,
   InOp[0] = N->getOperand(0);
   InOp[1] = N->getOperand(1);  
 
-  switch (N->getOpcode())
+  switch (N->getOpcode()) {
-  {
     case ISD::ADD:
       if (InOp[0].getOpcode() == ISD::Constant &&
           InOp[1].getOpcode() == ISD::Constant) {
@@ -424,12 +391,15 @@ PIC16TargetLowering::LowerADDSUB(SDNode *N, SelectionDAG &DAG,
         ConstantSDNode *CST1 = dyn_cast<ConstantSDNode>(InOp[1]);
         return DAG.getConstant(CST0->getValue() + CST1->getValue(), MVT::i16);
       }
+      break;
+
     case ISD::ADDE:
     case ISD::ADDC:
       AS  = ISD::ADD;
       ASE = ISD::ADDE;
       ASC = ISD::ADDC;
       break;
+
     case ISD::SUB:
       if (InOp[0].getOpcode() == ISD::Constant &&
           InOp[1].getOpcode() == ISD::Constant) {
@@ -437,13 +407,15 @@ PIC16TargetLowering::LowerADDSUB(SDNode *N, SelectionDAG &DAG,
         ConstantSDNode *CST1 = dyn_cast<ConstantSDNode>(InOp[1]);
         return DAG.getConstant(CST0->getValue() - CST1->getValue(), MVT::i16);
       }
+      break;
+
     case ISD::SUBE:
     case ISD::SUBC:
       AS  = ISD::SUB;
       ASE = ISD::SUBE;
       ASC = ISD::SUBC;
       break;
-    }
+  } // end switch.
 
   assert ((N->getValueType(0) == MVT::i16) 
            && "expecting an MVT::i16 node for lowering");
@@ -453,7 +425,7 @@ PIC16TargetLowering::LowerADDSUB(SDNode *N, SelectionDAG &DAG,
 
   for (i = 0; i < 2; i++) {
     if (InOp[i].getOpcode() == ISD::GlobalAddress) {
-      //we don't want to lower subs/adds with global address (at least not yet)
+      // We don't want to lower subs/adds with global address yet.
       return SDOperand();
     }
     else if (InOp[i].getOpcode() == ISD::Constant) {
@@ -469,11 +441,11 @@ PIC16TargetLowering::LowerADDSUB(SDNode *N, SelectionDAG &DAG,
     else if (InOp[i].getOpcode() == ISD::LOAD) {
       changed = true;
       // LowerLOAD returns a Package node or it may combine and return 
-      // anything else
+      // anything else.
       SDOperand lowered = LowerLOAD(InOp[i].Val, DAG, DCI);
 
       // So If LowerLOAD returns something other than Package, 
-      // then just call ADD again
+      // then just call ADD again.
       if (lowered.getOpcode() != PIC16ISD::Package)
         return LowerADDSUB(N, DAG, DCI);
           
@@ -487,15 +459,15 @@ PIC16TargetLowering::LowerADDSUB(SDNode *N, SelectionDAG &DAG,
              (InOp[i].getOpcode() == ISD::SUBE) ||
              (InOp[i].getOpcode() == ISD::SUBC)) {
       changed = true;
-      //must call LowerADDSUB recursively here....
+      // Must call LowerADDSUB recursively here,
-      //LowerADDSUB returns a Package node
+      // LowerADDSUB returns a Package node.
       SDOperand lowered = LowerADDSUB(InOp[i].Val, DAG, DCI);
 
       LoOps[i] = lowered.getOperand(0);
       HiOps[i] = lowered.getOperand(1);
     }
     else if (InOp[i].getOpcode() == ISD::SIGN_EXTEND) {
-      //FIXME: I am just zero extending. for now.
+      // FIXME: I am just zero extending. for now.
       changed = true;
       LoOps[i] = InOp[i].getOperand(0);
       HiOps[i] = DAG.getConstant(0, MVT::i8);
@@ -505,14 +477,14 @@ PIC16TargetLowering::LowerADDSUB(SDNode *N, SelectionDAG &DAG,
       DAG.viewGraph();
       assert (0 && "not implemented yet");
     }
-  } //end for
+  } // end for.
 
   assert (changed && "nothing changed while lowering SUBx/ADDx");
 
   VTList = DAG.getVTList(MVT::i8, MVT::Flag);
   if (N->getOpcode() == ASE) { 
-    //we must take in the existing carry
+    // We must take in the existing carry
-    //if this node is part of an existing subx/addx sequence
+    // if this node is part of an existing subx/addx sequence.
     LoOps[2] = N->getOperand(2).getValue(1);
     as1 = DAG.getNode (ASE, VTList, LoOps, 3);
   }
@@ -521,11 +493,11 @@ PIC16TargetLowering::LowerADDSUB(SDNode *N, SelectionDAG &DAG,
   }
   HiOps[2] = as1.getValue(1);
   as2 = DAG.getNode (ASE, VTList, HiOps, 3);
-  //we must build a pair that also provides the carry from sube/adde
+  // We must build a pair that also provides the carry from sube/adde.
   OutOps[0] = as1;
   OutOps[1] = as2;
   OutOps[2] = as2.getValue(1);
-  //breaking an original i16 so lets make the Package also an i16
+  // Breaking an original i16, so lets make the Package also an i16.
   if (N->getOpcode() == ASE) {
     VTList = DAG.getVTList(MVT::i16, MVT::Flag);
     retVal = DAG.getNode (PIC16ISD::Package, VTList, OutOps, 3);
@@ -548,13 +520,6 @@ PIC16TargetLowering::LowerADDSUB(SDNode *N, SelectionDAG &DAG,
 
 //===----------------------------------------------------------------------===//
 //                      Calling Convention Implementation
-//
-//  The lower operations present on calling convention works on this order:
-//      LowerCALL (virt regs --> phys regs, virt regs --> stack) 
-//      LowerFORMAL_ARGUMENTS (phys --> virt regs, stack --> virt regs)
-//      LowerRET (virt regs --> phys regs)
-//      LowerCALL (phys regs --> virt regs)
-//
 //===----------------------------------------------------------------------===//
 
 #include "PIC16GenCallingConv.inc"
@@ -574,7 +539,7 @@ LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG)
   SDOperand Root = Op.getOperand(0);
 
   // Return the new list of results.
-  // Just copy right now.
+  // FIXME: Just copy right now.
   ArgValues.push_back(Root);
 
   return DAG.getNode(ISD::MERGE_VALUES, Op.Val->getVTList(), &ArgValues[0], 
@@ -601,19 +566,23 @@ SDOperand PIC16TargetLowering::PerformDAGCombine(SDNode *N,
   ConstantSDNode *CST;
   SelectionDAG &DAG = DCI.DAG;
 
-  switch (N->getOpcode()) 
+  switch (N->getOpcode()) {
-  {
+    default: 
-  default: break;
+      break;
-  case PIC16ISD::Package  :
+
-    cout <<"==== combining PIC16ISD::Package\n";
+    case PIC16ISD::Package:
+      DOUT << "==== combining PIC16ISD::Package\n";
       return SDOperand();
-  case ISD::ADD  :
+
-  case ISD::SUB  :
+    case ISD::ADD:
+    case ISD::SUB:
       if ((N->getOperand(0).getOpcode() == ISD::GlobalAddress) ||
           (N->getOperand(0).getOpcode() == ISD::FrameIndex)) {
-      //do not touch pointer adds
+        // Do not touch pointer adds.
         return SDOperand ();
       }
+      break;
+
     case ISD::ADDE :
     case ISD::ADDC :
     case ISD::SUBE :
@@ -622,11 +591,11 @@ SDOperand PIC16TargetLowering::PerformDAGCombine(SDNode *N,
         SDOperand retVal = LowerADDSUB(N, DAG,DCI); 
         // LowerADDSUB has already combined the result, 
         // so we just return nothing to avoid assertion failure from llvm 
-      // if N has been deleted already
+        // if N has been deleted already.
         return SDOperand();
       }
       else if (N->getValueType(0) == MVT::i8) { 
-      //sanity check ....
+        // Sanity check ....
         for (int i=0; i<2; i++) {
           if (N->getOperand (i).getOpcode() == PIC16ISD::Package) {
             assert (0 && 
@@ -635,6 +604,8 @@ SDOperand PIC16TargetLowering::PerformDAGCombine(SDNode *N,
         }
       }
       break;
+
+    // FIXME: split this large chunk of code.
     case ISD::STORE :
     {
       SDOperand Chain = N->getOperand(0);  
@@ -644,7 +615,6 @@ SDOperand PIC16TargetLowering::PerformDAGCombine(SDNode *N,
       int NUM_STORES;
       SDOperand Stores[6];
 
-
       // if source operand is expected to be extended to 
       // some higher type then - remove this extension 
       // SDNode and do the extension manually
@@ -656,16 +626,18 @@ SDOperand PIC16TargetLowering::PerformDAGCombine(SDNode *N,
         return Stores[0];
       }
 
-    switch(Src.getValueType()) 
+      switch(Src.getValueType()) {
-    {
         case MVT::i8:  
           break;
+
         case MVT::i16: 
           NUM_STORES = 2;
           break;
+
         case MVT::i32: 
           NUM_STORES = 4;
           break;
+
         case MVT::i64: 
           NUM_STORES = 8; 
           break;
@@ -690,8 +662,7 @@ SDOperand PIC16TargetLowering::PerformDAGCombine(SDNode *N,
         return Chain;
       }
       else if (isa<GlobalAddressSDNode>(Dest) && isa<ConstantSDNode>(Src) 
-             && (Src.getValueType() != MVT::i8))
+               && (Src.getValueType() != MVT::i8)) {
-    {
         //create direct addressing a = CONST
         CST = dyn_cast<ConstantSDNode>(Src);
         for (i = 0; i < NUM_STORES; i++) {
@@ -708,7 +679,7 @@ SDOperand PIC16TargetLowering::PerformDAGCombine(SDNode *N,
       }
       else if (isa<LoadSDNode>(Dest) && isa<ConstantSDNode>(Src) 
               && (Src.getValueType() != MVT::i8)) {
-      //create indirect addressing
+        // Create indirect addressing.
         CST = dyn_cast<ConstantSDNode>(Src);
         Chain = Dest.getOperand(0);  
         SDOperand Load;
@@ -740,7 +711,8 @@ SDOperand PIC16TargetLowering::PerformDAGCombine(SDNode *N,
           toWorkList = DAG.getNode(ISD::ADD, MVT::i16, Dest,
                                    DAG.getConstant(1, MVT::i16));
           Stores[1] = DAG.getStore(Chain, Src.getOperand(0), Dest, NULL, 0);
-        Stores[0] = DAG.getStore(Chain, Src.getOperand(1), toWorkList, NULL, 0);
+          Stores[0] = DAG.getStore(Chain, Src.getOperand(1), toWorkList, NULL, 
+                                   0);
 
           // We want to merge sequence of add with constant to one add and a 
           // constant, so add the ADD node to worklist to have llvm do that 
@@ -757,28 +729,19 @@ SDOperand PIC16TargetLowering::PerformDAGCombine(SDNode *N,
       else if (Src.getOpcode() == ISD::TRUNCATE) {
       }
       else {
-      // DAG.setGraphColor(N, "blue");
-      // DAG.viewGraph();
-      // assert (0 && "input to store not implemented yet");
       }
-  } //end ISD::STORE
+    } // end ISD::STORE.
-
     break;
+
     case ISD::LOAD :
     {
       SDOperand Ptr = N->getOperand(1);
       if (Ptr.getOpcode() == PIC16ISD::Package) {
-      // DAG.setGraphColor(N, "blue");
-      // DAG.viewGraph();
-      // Here we must make so that:
-      // Ptr.getOperand(0) --> fsrl
-      // Ptr.getOperand(1) --> fsrh
         assert (0 && "not implemented yet");
        }
-     //return SDOperand();
-     //break;
     }
-  }//end switch
+    break;
+  } // end switch.
 
   return SDOperand();
 }

lib/Target/PIC16/PIC16ISelLowering.h

@@ -15,10 +15,10 @@
 #ifndef PIC16ISELLOWERING_H
 #define PIC16ISELLOWERING_H
 
-#include "llvm/CodeGen/SelectionDAG.h"
-#include "llvm/Target/TargetLowering.h"
 #include "PIC16.h"
 #include "PIC16Subtarget.h"
+#include "llvm/CodeGen/SelectionDAG.h"
+#include "llvm/Target/TargetLowering.h"
 
 namespace llvm {
   namespace PIC16ISD {

lib/Target/PIC16/PIC16InstrInfo.cpp

@@ -21,7 +21,7 @@
 
 using namespace llvm;
 
-// TODO: Add the subtarget support on this constructor.
+// FIXME: Add the subtarget support on this constructor.
 PIC16InstrInfo::PIC16InstrInfo(PIC16TargetMachine &tm)
   : TargetInstrInfoImpl(PIC16Insts, array_lengthof(PIC16Insts)),
     TM(tm), RI(*this) {}
@@ -134,7 +134,7 @@ InsertBranch(MachineBasicBlock &MBB,
     return 1;
   }
 
-  // TODO: If the there are some conditions specified then conditional branch 
+  // FIXME: If the there are some conditions specified then conditional branch 
   // should be generated.
   // For the time being no instruction is being generated therefore 
   // returning NULL.

lib/Target/PIC16/PIC16InstrInfo.td

@@ -74,7 +74,7 @@ class ArithI<bits<6> op, string instr_asm, SDNode OpNode,
       !strconcat(instr_asm, " $c"),
       [(set CPURegs:$dst, (OpNode CPURegs:$b, Od:$c))]>;
 
-// Memory Load/Store 
+// Memory Load/Store. 
 class LoadDirect<bits<6> op, string instr_asm, PatFrag OpNode>:
   ByteFormat< op,
       (outs CPURegs:$dst),
@@ -103,7 +103,7 @@ class StoreInDirect<bits<6> op, string instr_asm, PatFrag OpNode>:
       !strconcat(instr_asm, " $fsr"),
       [(OpNode CPURegs:$src, PTRRegs:$fsr)]>;
 
-// Move 
+// Move.
 class MovLit<bits<6> op, string instr_asm>:
   LiteralFormat< op,
       (outs CPURegs:$dst),

lib/Target/PIC16/PIC16RegisterInfo.cpp

@@ -34,7 +34,7 @@
 
 using namespace llvm;
 
-// TODO: add subtarget support
+// FIXME: add subtarget support.
 PIC16RegisterInfo::PIC16RegisterInfo(const TargetInstrInfo &tii)
   : PIC16GenRegisterInfo(PIC16::ADJCALLSTACKDOWN, PIC16::ADJCALLSTACKUP),
   TII(tii) {}
@@ -70,7 +70,6 @@ MachineInstr *PIC16RegisterInfo::
 foldMemoryOperand(MachineInstr* MI, unsigned OpNum, int FI) const 
 {
   MachineInstr *NewMI = NULL;
-
   return NewMI;
 }
 
@@ -152,27 +151,24 @@ eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
   int stackSize  = MF.getFrameInfo()->getStackSize();
   int spOffset   = MF.getFrameInfo()->getObjectOffset(FrameIndex);
 
-  #ifndef NDEBUG
   DOUT << "\nFunction : " << MF.getFunction()->getName() << "\n";
   DOUT << "<--------->\n";
+#ifndef NDEBUG
   MI.print(DOUT);
+#endif
   DOUT << "FrameIndex : " << FrameIndex << "\n";
   DOUT << "spOffset   : " << spOffset << "\n";
   DOUT << "stackSize  : " << stackSize << "\n";
-  #endif
 
-  // as explained on LowerFORMAL_ARGUMENTS, detect negative offsets 
+  // As explained on LowerFORMAL_ARGUMENTS, detect negative offsets 
   // and adjust SPOffsets considering the final stack size.
   int Offset = ((spOffset < 0) ? (stackSize + (-(spOffset+4))) : (spOffset));
-  //Offset    += MI.getOperand(i+1).getImm();
 
-  #ifndef NDEBUG
   DOUT << "Offset     : " << Offset << "\n";
   DOUT << "<--------->\n";
-  #endif
 
   // MI.getOperand(i+1).ChangeToImmediate(Offset);
-   MI.getOperand(i).ChangeToRegister(getFrameRegister(MF),false);
+  MI.getOperand(i).ChangeToRegister(getFrameRegister(MF), false);
 }
 
 void PIC16RegisterInfo::
@@ -186,7 +182,8 @@ emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const
 }
 
 void PIC16RegisterInfo::
-processFunctionBeforeFrameFinalized(MachineFunction &MF) const {
+processFunctionBeforeFrameFinalized(MachineFunction &MF) const 
+{
 }
 
 unsigned PIC16RegisterInfo::

lib/Target/PIC16/PIC16Subtarget.cpp

@@ -11,8 +11,8 @@
 //
 //===----------------------------------------------------------------------===//
 
-#include "PIC16Subtarget.h"
 #include "PIC16.h"
+#include "PIC16Subtarget.h"
 #include "PIC16GenSubtarget.inc"
 using namespace llvm;
 

lib/Target/PIC16/PIC16Subtarget.h

@@ -14,8 +14,8 @@
 #ifndef PIC16SUBTARGET_H
 #define PIC16SUBTARGET_H
 
-#include "llvm/Target/TargetSubtarget.h"
 #include "llvm/Target/TargetMachine.h"
+#include "llvm/Target/TargetSubtarget.h"
 
 #include <string>
 

lib/Target/PIC16/PIC16TargetMachine.cpp

@@ -12,12 +12,12 @@
 //===----------------------------------------------------------------------===//
 
 #include "PIC16.h"
-#include "PIC16TargetMachine.h"
 #include "PIC16TargetAsmInfo.h"
+#include "PIC16TargetMachine.h"
 #include "llvm/Module.h"
 #include "llvm/PassManager.h"
-#include "llvm/Target/TargetMachineRegistry.h"
 #include "llvm/Target/TargetAsmInfo.h"
+#include "llvm/Target/TargetMachineRegistry.h"
 
 using namespace llvm;
 
@@ -33,8 +33,7 @@ PIC16TargetMachine(const Module &M, const std::string &FS) :
   FrameInfo(TargetFrameInfo::StackGrowsUp, 8, 0) { }
 
 
-const TargetAsmInfo *PIC16TargetMachine::
+const TargetAsmInfo *PIC16TargetMachine::createTargetAsmInfo() const 
-createTargetAsmInfo() const 
 {
   return new PIC16TargetAsmInfo(*this);
 }
@@ -43,8 +42,7 @@ createTargetAsmInfo() const
 // Pass Pipeline Configuration
 //===----------------------------------------------------------------------===//
 
-bool PIC16TargetMachine::
+bool PIC16TargetMachine::addInstSelector(PassManagerBase &PM, bool Fast) 
-addInstSelector(PassManagerBase &PM, bool Fast) 
 {
   // Install an instruction selector.
   PM.add(createPIC16ISelDag(*this));
@@ -57,7 +55,7 @@ addPrologEpilogInserter(PassManagerBase &PM, bool Fast)
   return false;
 }
 
-bool PIC16TargetMachine:: addPreEmitPass(PassManagerBase &PM, bool Fast) 
+bool PIC16TargetMachine::addPreEmitPass(PassManagerBase &PM, bool Fast) 
 {
   return true;
 }