6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-12-28 19:31:58 +00:00
Code Issues Projects Releases Wiki Activity

Precompute a bit vector of register sub-classes.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140827 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen 2011-09-30 00:10:40 +00:00
parent 7dcaa5b0fb
commit 203e0b17dd
2 changed files with 35 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

29
utils/TableGen/CodeGenRegisters.cpp
View File

@ -388,6 +388,34 @@ const std::string &CodeGenRegisterClass::getName() const {
return TheDef->getName(); return TheDef->getName();
} }
// Compute sub-classes of all register classes.
// Assume the classes are ordered topologically.
void CodeGenRegisterClass::
computeSubClasses(ArrayRef<CodeGenRegisterClass*> RegClasses) {
// Visit backwards so sub-classes are seen first.
for (unsigned rci = RegClasses.size(); rci; --rci) {
CodeGenRegisterClass &RC = *RegClasses[rci - 1];
RC.SubClasses.resize(RegClasses.size());
RC.SubClasses.set(RC.EnumValue);
// Normally, all subclasses have IDs >= rci, unless RC is part of a clique.
for (unsigned s = rci; s != RegClasses.size(); ++s) {
if (RC.SubClasses.test(s))
continue;
CodeGenRegisterClass *SubRC = RegClasses[s];
if (!RC.hasSubClass(SubRC))
continue;
// SubRC is a sub-class. Grap all its sub-classes so we won't have to
// check them again.
RC.SubClasses |= SubRC->SubClasses;
}
// Sweep up missed clique members. They will be immediately preceeding RC.
for (unsigned s = rci - 1; s && RC.hasSubClass(RegClasses[s - 1]); --s)
RC.SubClasses.set(s - 1);
}
}
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// CodeGenRegBank // CodeGenRegBank
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
@ -435,6 +463,7 @@ CodeGenRegBank::CodeGenRegBank(RecordKeeper &Records) : Records(Records) {
array_pod_sort(RegClasses.begin(), RegClasses.end(), TopoOrderRC); array_pod_sort(RegClasses.begin(), RegClasses.end(), TopoOrderRC);
for (unsigned i = 0, e = RegClasses.size(); i != e; ++i) for (unsigned i = 0, e = RegClasses.size(); i != e; ++i)
RegClasses[i]->EnumValue = i; RegClasses[i]->EnumValue = i;
CodeGenRegisterClass::computeSubClasses(RegClasses);
} }
CodeGenRegister *CodeGenRegBank::getReg(Record *Def) { CodeGenRegister *CodeGenRegBank::getReg(Record *Def) {

6
utils/TableGen/CodeGenRegisters.h
View File

@ -19,6 +19,7 @@
#include "SetTheory.h" #include "SetTheory.h"
#include "llvm/CodeGen/ValueTypes.h" #include "llvm/CodeGen/ValueTypes.h"
#include "llvm/ADT/ArrayRef.h" #include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/BitVector.h"
#include "llvm/ADT/DenseMap.h" #include "llvm/ADT/DenseMap.h"
#include "llvm/ADT/SetVector.h" #include "llvm/ADT/SetVector.h"
#include <cstdlib> #include <cstdlib>
@ -87,6 +88,8 @@ namespace llvm {
CodeGenRegister::Set Members; CodeGenRegister::Set Members;
const std::vector<Record*> *Elements; const std::vector<Record*> *Elements;
std::vector<SmallVector<Record*, 16> > AltOrders; std::vector<SmallVector<Record*, 16> > AltOrders;
// Bit mask of sub-classes including this, indexed by their EnumValue.
BitVector SubClasses;
public: public:
Record *TheDef; Record *TheDef;
unsigned EnumValue; unsigned EnumValue;
@ -139,6 +142,9 @@ namespace llvm {
unsigned getNumOrders() const { return 1 + AltOrders.size(); } unsigned getNumOrders() const { return 1 + AltOrders.size(); }
CodeGenRegisterClass(CodeGenRegBank&, Record *R); CodeGenRegisterClass(CodeGenRegBank&, Record *R);
// Called by CodeGenRegBank::CodeGenRegBank().
static void computeSubClasses(ArrayRef<CodeGenRegisterClass*>);
}; };
// CodeGenRegBank - Represent a target's registers and the relations between // CodeGenRegBank - Represent a target's registers and the relations between