mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-01-25 00:33:15 +00:00
Make first of several changes to bring up to AArch64 fast-isel style
Summary: Make Mips fast-isel track the form of AArch64 where practical. This makes it easier for people to review the code, to borrow similar code, and to see how to eventually move a lot of this target code for fast-isels into target independent code. These are just cosmetic changes. Should be no functional difference. Test Plan: make check test-suite for 4 flavors mips32 r1/r2 , -O0/-O2 Reviewers: dsanders Reviewed By: dsanders Subscribers: aemerson, llvm-commits, rfuhler Differential Revision: http://reviews.llvm.org/D5595 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219633 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Reed Kotler
parent
9de9951e15
commit
2061a56b8a
@ -18,23 +18,44 @@ using namespace llvm;
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namespace {
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// All possible address modes.
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typedef struct Address {
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enum { RegBase, FrameIndexBase } BaseType;
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union {
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unsigned Reg;
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int FI;
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} Base;
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int64_t Offset;
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// Innocuous defaults for our address.
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Address() : BaseType(RegBase), Offset(0) { Base.Reg = 0; }
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} Address;
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class MipsFastISel final : public FastISel {
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// All possible address modes.
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class Address {
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public:
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typedef enum { RegBase, FrameIndexBase } BaseKind;
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private:
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BaseKind Kind;
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union {
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unsigned Reg;
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int FI;
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} Base;
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int64_t Offset;
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const GlobalValue *GV;
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public:
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// Innocuous defaults for our address.
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Address() : Kind(RegBase), Offset(0), GV(0) { Base.Reg = 0; }
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void setKind(BaseKind K) { Kind = K; }
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BaseKind getKind() const { return Kind; }
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bool isRegBase() const { return Kind == RegBase; }
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void setReg(unsigned Reg) {
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assert(isRegBase() && "Invalid base register access!");
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Base.Reg = Reg;
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}
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unsigned getReg() const {
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assert(isRegBase() && "Invalid base register access!");
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return Base.Reg;
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}
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void setOffset(int64_t Offset_) { Offset = Offset_; }
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int64_t getOffset() const { return Offset; }
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void setGlobalValue(const GlobalValue *G) { GV = G; }
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const GlobalValue *getGlobalValue() { return GV; }
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};
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/// Subtarget - Keep a pointer to the MipsSubtarget around so that we can
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/// make the right decision when generating code for different targets.
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Module &M;
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@ -48,9 +69,80 @@ class MipsFastISel final : public FastISel {
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LLVMContext *Context;
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bool TargetSupported;
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bool UnsupportedFPMode;
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bool UnsupportedFPMode; // To allow fast-isel to proceed and just not handle
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// floating point but not reject doing fast-isel in other
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// situations
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private:
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// Selection routines.
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bool selectLoad(const Instruction *I);
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bool selectStore(const Instruction *I);
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bool selectBranch(const Instruction *I);
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bool selectCmp(const Instruction *I);
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bool selectFPExt(const Instruction *I);
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bool selectFPTrunc(const Instruction *I);
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bool selectFPToInt(const Instruction *I, bool IsSigned);
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bool selectRet(const Instruction *I);
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bool selectTrunc(const Instruction *I);
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bool selectIntExt(const Instruction *I);
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// Utility helper routines.
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bool isTypeLegal(Type *Ty, MVT &VT);
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bool isLoadTypeLegal(Type *Ty, MVT &VT);
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bool computeAddress(const Value *Obj, Address &Addr);
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// Emit helper routines.
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bool emitCmp(unsigned DestReg, const CmpInst *CI);
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bool emitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
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unsigned Alignment = 0);
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bool emitStore(MVT VT, unsigned SrcReg, Address &Addr,
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unsigned Alignment = 0);
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bool emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg,
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bool IsZExt);
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bool emitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
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bool emitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
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bool emitIntSExt32r1(MVT SrcVT, unsigned SrcReg, MVT DestVT,
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unsigned DestReg);
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bool emitIntSExt32r2(MVT SrcVT, unsigned SrcReg, MVT DestVT,
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unsigned DestReg);
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unsigned getRegEnsuringSimpleIntegerWidening(const Value *, bool IsUnsigned);
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unsigned materializeFP(const ConstantFP *CFP, MVT VT);
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unsigned materializeGV(const GlobalValue *GV, MVT VT);
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unsigned materializeInt(const Constant *C, MVT VT);
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unsigned materialize32BitInt(int64_t Imm, const TargetRegisterClass *RC);
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MachineInstrBuilder emitInst(unsigned Opc) {
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return BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc));
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}
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MachineInstrBuilder emitInst(unsigned Opc, unsigned DstReg) {
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return BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc),
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DstReg);
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}
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MachineInstrBuilder emitInstStore(unsigned Opc, unsigned SrcReg,
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unsigned MemReg, int64_t MemOffset) {
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return emitInst(Opc).addReg(SrcReg).addReg(MemReg).addImm(MemOffset);
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}
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MachineInstrBuilder emitInstLoad(unsigned Opc, unsigned DstReg,
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unsigned MemReg, int64_t MemOffset) {
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return emitInst(Opc, DstReg).addReg(MemReg).addImm(MemOffset);
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}
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// for some reason, this default is not generated by tablegen
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// so we explicitly generate it here.
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//
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unsigned fastEmitInst_riir(uint64_t inst, const TargetRegisterClass *RC,
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unsigned Op0, bool Op0IsKill, uint64_t imm1,
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uint64_t imm2, unsigned Op3, bool Op3IsKill) {
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return 0;
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}
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public:
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// Backend specific FastISel code.
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explicit MipsFastISel(FunctionLoweringInfo &funcInfo,
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const TargetLibraryInfo *libInfo)
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: FastISel(funcInfo, libInfo),
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@ -67,78 +159,12 @@ public:
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UnsupportedFPMode = Subtarget->isFP64bit();
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}
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bool fastSelectInstruction(const Instruction *I) override;
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unsigned fastMaterializeConstant(const Constant *C) override;
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bool ComputeAddress(const Value *Obj, Address &Addr);
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private:
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bool EmitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
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unsigned Alignment = 0);
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bool EmitStore(MVT VT, unsigned SrcReg, Address &Addr,
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unsigned Alignment = 0);
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bool EmitCmp(unsigned DestReg, const CmpInst *CI);
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bool SelectLoad(const Instruction *I);
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bool SelectBranch(const Instruction *I);
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bool SelectRet(const Instruction *I);
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bool SelectStore(const Instruction *I);
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bool SelectIntExt(const Instruction *I);
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bool SelectTrunc(const Instruction *I);
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bool SelectFPExt(const Instruction *I);
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bool SelectFPTrunc(const Instruction *I);
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bool SelectFPToI(const Instruction *I, bool IsSigned);
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bool SelectCmp(const Instruction *I);
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bool isTypeLegal(Type *Ty, MVT &VT);
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bool isLoadTypeLegal(Type *Ty, MVT &VT);
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unsigned getRegEnsuringSimpleIntegerWidening(const Value *, bool IsUnsigned);
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unsigned MaterializeFP(const ConstantFP *CFP, MVT VT);
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unsigned MaterializeGV(const GlobalValue *GV, MVT VT);
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unsigned MaterializeInt(const Constant *C, MVT VT);
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unsigned Materialize32BitInt(int64_t Imm, const TargetRegisterClass *RC);
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bool EmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg,
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bool IsZExt);
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bool EmitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
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bool EmitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
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bool EmitIntSExt32r1(MVT SrcVT, unsigned SrcReg, MVT DestVT,
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unsigned DestReg);
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bool EmitIntSExt32r2(MVT SrcVT, unsigned SrcReg, MVT DestVT,
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unsigned DestReg);
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// for some reason, this default is not generated by tablegen
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// so we explicitly generate it here.
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//
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unsigned fastEmitInst_riir(uint64_t inst, const TargetRegisterClass *RC,
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unsigned Op0, bool Op0IsKill, uint64_t imm1,
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uint64_t imm2, unsigned Op3, bool Op3IsKill) {
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return 0;
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}
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MachineInstrBuilder EmitInst(unsigned Opc) {
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return BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc));
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}
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MachineInstrBuilder EmitInst(unsigned Opc, unsigned DstReg) {
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return BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc),
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DstReg);
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}
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MachineInstrBuilder EmitInstStore(unsigned Opc, unsigned SrcReg,
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unsigned MemReg, int64_t MemOffset) {
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return EmitInst(Opc).addReg(SrcReg).addReg(MemReg).addImm(MemOffset);
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}
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MachineInstrBuilder EmitInstLoad(unsigned Opc, unsigned DstReg,
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unsigned MemReg, int64_t MemOffset) {
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return EmitInst(Opc, DstReg).addReg(MemReg).addImm(MemOffset);
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}
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bool fastSelectInstruction(const Instruction *I) override;
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#include "MipsGenFastISel.inc"
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};
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} // end anonymous namespace.
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bool MipsFastISel::isTypeLegal(Type *Ty, MVT &VT) {
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EVT evt = TLI.getValueType(Ty, true);
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@ -163,7 +189,7 @@ bool MipsFastISel::isLoadTypeLegal(Type *Ty, MVT &VT) {
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return false;
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}
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bool MipsFastISel::ComputeAddress(const Value *Obj, Address &Addr) {
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bool MipsFastISel::computeAddress(const Value *Obj, Address &Addr) {
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// This construct looks a big awkward but it is how other ports handle this
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// and as this function is more fully completed, these cases which
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// return false will have additional code in them.
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@ -172,8 +198,8 @@ bool MipsFastISel::ComputeAddress(const Value *Obj, Address &Addr) {
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return false;
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else if (isa<ConstantExpr>(Obj))
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return false;
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Addr.Base.Reg = getRegForValue(Obj);
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return Addr.Base.Reg != 0;
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Addr.setReg(getRegForValue(Obj));
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return Addr.getReg() != 0;
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}
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unsigned MipsFastISel::getRegEnsuringSimpleIntegerWidening(const Value *V,
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@ -184,14 +210,14 @@ unsigned MipsFastISel::getRegEnsuringSimpleIntegerWidening(const Value *V,
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MVT VMVT = TLI.getValueType(V->getType(), true).getSimpleVT();
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if ((VMVT == MVT::i8) || (VMVT == MVT::i16)) {
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unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
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if (!EmitIntExt(VMVT, VReg, MVT::i32, TempReg, IsUnsigned))
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if (!emitIntExt(VMVT, VReg, MVT::i32, TempReg, IsUnsigned))
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return 0;
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VReg = TempReg;
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}
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return VReg;
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}
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bool MipsFastISel::EmitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
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bool MipsFastISel::emitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
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unsigned Alignment) {
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//
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// more cases will be handled here in following patches.
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@ -230,7 +256,7 @@ bool MipsFastISel::EmitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
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default:
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return false;
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}
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EmitInstLoad(Opc, ResultReg, Addr.Base.Reg, Addr.Offset);
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emitInstLoad(Opc, ResultReg, Addr.getReg(), Addr.getOffset());
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return true;
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}
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@ -245,16 +271,16 @@ unsigned MipsFastISel::fastMaterializeConstant(const Constant *C) {
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MVT VT = CEVT.getSimpleVT();
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if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
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return (UnsupportedFPMode) ? 0 : MaterializeFP(CFP, VT);
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return (UnsupportedFPMode) ? 0 : materializeFP(CFP, VT);
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else if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
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return MaterializeGV(GV, VT);
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return materializeGV(GV, VT);
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else if (isa<ConstantInt>(C))
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return MaterializeInt(C, VT);
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return materializeInt(C, VT);
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return 0;
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}
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bool MipsFastISel::EmitStore(MVT VT, unsigned SrcReg, Address &Addr,
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bool MipsFastISel::emitStore(MVT VT, unsigned SrcReg, Address &Addr,
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unsigned Alignment) {
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//
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// more cases will be handled here in following patches.
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@ -283,11 +309,11 @@ bool MipsFastISel::EmitStore(MVT VT, unsigned SrcReg, Address &Addr,
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default:
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return false;
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}
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EmitInstStore(Opc, SrcReg, Addr.Base.Reg, Addr.Offset);
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emitInstStore(Opc, SrcReg, Addr.getReg(), Addr.getOffset());
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return true;
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}
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bool MipsFastISel::EmitIntSExt32r1(MVT SrcVT, unsigned SrcReg, MVT DestVT,
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bool MipsFastISel::emitIntSExt32r1(MVT SrcVT, unsigned SrcReg, MVT DestVT,
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unsigned DestReg) {
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unsigned ShiftAmt;
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switch (SrcVT.SimpleTy) {
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@ -301,55 +327,55 @@ bool MipsFastISel::EmitIntSExt32r1(MVT SrcVT, unsigned SrcReg, MVT DestVT,
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break;
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}
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unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
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EmitInst(Mips::SLL, TempReg).addReg(SrcReg).addImm(ShiftAmt);
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EmitInst(Mips::SRA, DestReg).addReg(TempReg).addImm(ShiftAmt);
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emitInst(Mips::SLL, TempReg).addReg(SrcReg).addImm(ShiftAmt);
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emitInst(Mips::SRA, DestReg).addReg(TempReg).addImm(ShiftAmt);
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return true;
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}
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bool MipsFastISel::EmitIntSExt32r2(MVT SrcVT, unsigned SrcReg, MVT DestVT,
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bool MipsFastISel::emitIntSExt32r2(MVT SrcVT, unsigned SrcReg, MVT DestVT,
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unsigned DestReg) {
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switch (SrcVT.SimpleTy) {
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default:
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return false;
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case MVT::i8:
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EmitInst(Mips::SEB, DestReg).addReg(SrcReg);
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emitInst(Mips::SEB, DestReg).addReg(SrcReg);
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break;
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case MVT::i16:
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EmitInst(Mips::SEH, DestReg).addReg(SrcReg);
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emitInst(Mips::SEH, DestReg).addReg(SrcReg);
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break;
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}
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return true;
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}
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bool MipsFastISel::EmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
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bool MipsFastISel::emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
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unsigned DestReg, bool IsZExt) {
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if (IsZExt)
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return EmitIntZExt(SrcVT, SrcReg, DestVT, DestReg);
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return EmitIntSExt(SrcVT, SrcReg, DestVT, DestReg);
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return emitIntZExt(SrcVT, SrcReg, DestVT, DestReg);
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return emitIntSExt(SrcVT, SrcReg, DestVT, DestReg);
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}
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bool MipsFastISel::EmitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
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bool MipsFastISel::emitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
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unsigned DestReg) {
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if ((DestVT != MVT::i32) && (DestVT != MVT::i16))
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return false;
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if (Subtarget->hasMips32r2())
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return EmitIntSExt32r2(SrcVT, SrcReg, DestVT, DestReg);
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return EmitIntSExt32r1(SrcVT, SrcReg, DestVT, DestReg);
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return emitIntSExt32r2(SrcVT, SrcReg, DestVT, DestReg);
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return emitIntSExt32r1(SrcVT, SrcReg, DestVT, DestReg);
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}
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bool MipsFastISel::EmitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
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bool MipsFastISel::emitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
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unsigned DestReg) {
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switch (SrcVT.SimpleTy) {
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default:
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return false;
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case MVT::i1:
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EmitInst(Mips::ANDi, DestReg).addReg(SrcReg).addImm(1);
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emitInst(Mips::ANDi, DestReg).addReg(SrcReg).addImm(1);
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break;
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case MVT::i8:
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EmitInst(Mips::ANDi, DestReg).addReg(SrcReg).addImm(0xff);
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emitInst(Mips::ANDi, DestReg).addReg(SrcReg).addImm(0xff);
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break;
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case MVT::i16:
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EmitInst(Mips::ANDi, DestReg).addReg(SrcReg).addImm(0xffff);
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emitInst(Mips::ANDi, DestReg).addReg(SrcReg).addImm(0xffff);
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break;
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}
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return true;
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@ -359,7 +385,7 @@ bool MipsFastISel::EmitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
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// This can cause a redundant sltiu to be generated.
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// FIXME: try and eliminate this in a future patch.
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//
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bool MipsFastISel::SelectBranch(const Instruction *I) {
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bool MipsFastISel::selectBranch(const Instruction *I) {
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const BranchInst *BI = cast<BranchInst>(I);
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MachineBasicBlock *BrBB = FuncInfo.MBB;
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//
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@ -375,7 +401,7 @@ bool MipsFastISel::SelectBranch(const Instruction *I) {
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// For now, just try the simplest case where it's fed by a compare.
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if (const CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) {
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unsigned CondReg = createResultReg(&Mips::GPR32RegClass);
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if (!EmitCmp(CondReg, CI))
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if (!emitCmp(CondReg, CI))
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return false;
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BuildMI(*BrBB, FuncInfo.InsertPt, DbgLoc, TII.get(Mips::BGTZ))
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.addReg(CondReg)
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@ -387,7 +413,7 @@ bool MipsFastISel::SelectBranch(const Instruction *I) {
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return false;
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}
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bool MipsFastISel::SelectLoad(const Instruction *I) {
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bool MipsFastISel::selectLoad(const Instruction *I) {
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// Atomic loads need special handling.
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if (cast<LoadInst>(I)->isAtomic())
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return false;
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@ -399,17 +425,17 @@ bool MipsFastISel::SelectLoad(const Instruction *I) {
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// See if we can handle this address.
|
||||
Address Addr;
|
||||
if (!ComputeAddress(I->getOperand(0), Addr))
|
||||
if (!computeAddress(I->getOperand(0), Addr))
|
||||
return false;
|
||||
|
||||
unsigned ResultReg;
|
||||
if (!EmitLoad(VT, ResultReg, Addr, cast<LoadInst>(I)->getAlignment()))
|
||||
if (!emitLoad(VT, ResultReg, Addr, cast<LoadInst>(I)->getAlignment()))
|
||||
return false;
|
||||
updateValueMap(I, ResultReg);
|
||||
return true;
|
||||
}
|
||||
|
||||
bool MipsFastISel::SelectStore(const Instruction *I) {
|
||||
bool MipsFastISel::selectStore(const Instruction *I) {
|
||||
Value *Op0 = I->getOperand(0);
|
||||
unsigned SrcReg = 0;
|
||||
|
||||
@ -429,15 +455,15 @@ bool MipsFastISel::SelectStore(const Instruction *I) {
|
||||
|
||||
// See if we can handle this address.
|
||||
Address Addr;
|
||||
if (!ComputeAddress(I->getOperand(1), Addr))
|
||||
if (!computeAddress(I->getOperand(1), Addr))
|
||||
return false;
|
||||
|
||||
if (!EmitStore(VT, SrcReg, Addr, cast<StoreInst>(I)->getAlignment()))
|
||||
if (!emitStore(VT, SrcReg, Addr, cast<StoreInst>(I)->getAlignment()))
|
||||
return false;
|
||||
return true;
|
||||
}
|
||||
|
||||
bool MipsFastISel::SelectRet(const Instruction *I) {
|
||||
bool MipsFastISel::selectRet(const Instruction *I) {
|
||||
const ReturnInst *Ret = cast<ReturnInst>(I);
|
||||
|
||||
if (!FuncInfo.CanLowerReturn)
|
||||
@ -445,12 +471,12 @@ bool MipsFastISel::SelectRet(const Instruction *I) {
|
||||
if (Ret->getNumOperands() > 0) {
|
||||
return false;
|
||||
}
|
||||
EmitInst(Mips::RetRA);
|
||||
emitInst(Mips::RetRA);
|
||||
return true;
|
||||
}
|
||||
|
||||
// Attempt to fast-select a floating-point extend instruction.
|
||||
bool MipsFastISel::SelectFPExt(const Instruction *I) {
|
||||
bool MipsFastISel::selectFPExt(const Instruction *I) {
|
||||
if (UnsupportedFPMode)
|
||||
return false;
|
||||
Value *Src = I->getOperand(0);
|
||||
@ -467,13 +493,13 @@ bool MipsFastISel::SelectFPExt(const Instruction *I) {
|
||||
return false;
|
||||
|
||||
unsigned DestReg = createResultReg(&Mips::AFGR64RegClass);
|
||||
EmitInst(Mips::CVT_D32_S, DestReg).addReg(SrcReg);
|
||||
emitInst(Mips::CVT_D32_S, DestReg).addReg(SrcReg);
|
||||
updateValueMap(I, DestReg);
|
||||
return true;
|
||||
}
|
||||
|
||||
// Attempt to fast-select a floating-point truncate instruction.
|
||||
bool MipsFastISel::SelectFPTrunc(const Instruction *I) {
|
||||
bool MipsFastISel::selectFPTrunc(const Instruction *I) {
|
||||
if (UnsupportedFPMode)
|
||||
return false;
|
||||
Value *Src = I->getOperand(0);
|
||||
@ -491,12 +517,12 @@ bool MipsFastISel::SelectFPTrunc(const Instruction *I) {
|
||||
if (!DestReg)
|
||||
return false;
|
||||
|
||||
EmitInst(Mips::CVT_S_D32, DestReg).addReg(SrcReg);
|
||||
emitInst(Mips::CVT_S_D32, DestReg).addReg(SrcReg);
|
||||
updateValueMap(I, DestReg);
|
||||
return true;
|
||||
}
|
||||
|
||||
bool MipsFastISel::SelectIntExt(const Instruction *I) {
|
||||
bool MipsFastISel::selectIntExt(const Instruction *I) {
|
||||
Type *DestTy = I->getType();
|
||||
Value *Src = I->getOperand(0);
|
||||
Type *SrcTy = Src->getType();
|
||||
@ -518,13 +544,13 @@ bool MipsFastISel::SelectIntExt(const Instruction *I) {
|
||||
MVT DestVT = DestEVT.getSimpleVT();
|
||||
unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
|
||||
|
||||
if (!EmitIntExt(SrcVT, SrcReg, DestVT, ResultReg, isZExt))
|
||||
if (!emitIntExt(SrcVT, SrcReg, DestVT, ResultReg, isZExt))
|
||||
return false;
|
||||
updateValueMap(I, ResultReg);
|
||||
return true;
|
||||
}
|
||||
|
||||
bool MipsFastISel::SelectTrunc(const Instruction *I) {
|
||||
bool MipsFastISel::selectTrunc(const Instruction *I) {
|
||||
// The high bits for a type smaller than the register size are assumed to be
|
||||
// undefined.
|
||||
Value *Op = I->getOperand(0);
|
||||
@ -549,7 +575,7 @@ bool MipsFastISel::SelectTrunc(const Instruction *I) {
|
||||
}
|
||||
|
||||
// Attempt to fast-select a floating-point-to-integer conversion.
|
||||
bool MipsFastISel::SelectFPToI(const Instruction *I, bool IsSigned) {
|
||||
bool MipsFastISel::selectFPToInt(const Instruction *I, bool IsSigned) {
|
||||
if (UnsupportedFPMode)
|
||||
return false;
|
||||
MVT DstVT, SrcVT;
|
||||
@ -587,9 +613,9 @@ bool MipsFastISel::SelectFPToI(const Instruction *I, bool IsSigned) {
|
||||
Opc = Mips::TRUNC_W_D32;
|
||||
|
||||
// Generate the convert.
|
||||
EmitInst(Opc, TempReg).addReg(SrcReg);
|
||||
emitInst(Opc, TempReg).addReg(SrcReg);
|
||||
|
||||
EmitInst(Mips::MFC1, DestReg).addReg(TempReg);
|
||||
emitInst(Mips::MFC1, DestReg).addReg(TempReg);
|
||||
|
||||
updateValueMap(I, DestReg);
|
||||
return true;
|
||||
@ -599,7 +625,7 @@ bool MipsFastISel::SelectFPToI(const Instruction *I, bool IsSigned) {
|
||||
// end up with redundant "andi" instructions after the sequences emitted below.
|
||||
// We should try and solve this issue in the future.
|
||||
//
|
||||
bool MipsFastISel::EmitCmp(unsigned ResultReg, const CmpInst *CI) {
|
||||
bool MipsFastISel::emitCmp(unsigned ResultReg, const CmpInst *CI) {
|
||||
const Value *Left = CI->getOperand(0), *Right = CI->getOperand(1);
|
||||
bool IsUnsigned = CI->isUnsigned();
|
||||
unsigned LeftReg = getRegEnsuringSimpleIntegerWidening(Left, IsUnsigned);
|
||||
@ -615,54 +641,54 @@ bool MipsFastISel::EmitCmp(unsigned ResultReg, const CmpInst *CI) {
|
||||
return false;
|
||||
case CmpInst::ICMP_EQ: {
|
||||
unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
|
||||
EmitInst(Mips::XOR, TempReg).addReg(LeftReg).addReg(RightReg);
|
||||
EmitInst(Mips::SLTiu, ResultReg).addReg(TempReg).addImm(1);
|
||||
emitInst(Mips::XOR, TempReg).addReg(LeftReg).addReg(RightReg);
|
||||
emitInst(Mips::SLTiu, ResultReg).addReg(TempReg).addImm(1);
|
||||
break;
|
||||
}
|
||||
case CmpInst::ICMP_NE: {
|
||||
unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
|
||||
EmitInst(Mips::XOR, TempReg).addReg(LeftReg).addReg(RightReg);
|
||||
EmitInst(Mips::SLTu, ResultReg).addReg(Mips::ZERO).addReg(TempReg);
|
||||
emitInst(Mips::XOR, TempReg).addReg(LeftReg).addReg(RightReg);
|
||||
emitInst(Mips::SLTu, ResultReg).addReg(Mips::ZERO).addReg(TempReg);
|
||||
break;
|
||||
}
|
||||
case CmpInst::ICMP_UGT: {
|
||||
EmitInst(Mips::SLTu, ResultReg).addReg(RightReg).addReg(LeftReg);
|
||||
emitInst(Mips::SLTu, ResultReg).addReg(RightReg).addReg(LeftReg);
|
||||
break;
|
||||
}
|
||||
case CmpInst::ICMP_ULT: {
|
||||
EmitInst(Mips::SLTu, ResultReg).addReg(LeftReg).addReg(RightReg);
|
||||
emitInst(Mips::SLTu, ResultReg).addReg(LeftReg).addReg(RightReg);
|
||||
break;
|
||||
}
|
||||
case CmpInst::ICMP_UGE: {
|
||||
unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
|
||||
EmitInst(Mips::SLTu, TempReg).addReg(LeftReg).addReg(RightReg);
|
||||
EmitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
|
||||
emitInst(Mips::SLTu, TempReg).addReg(LeftReg).addReg(RightReg);
|
||||
emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
|
||||
break;
|
||||
}
|
||||
case CmpInst::ICMP_ULE: {
|
||||
unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
|
||||
EmitInst(Mips::SLTu, TempReg).addReg(RightReg).addReg(LeftReg);
|
||||
EmitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
|
||||
emitInst(Mips::SLTu, TempReg).addReg(RightReg).addReg(LeftReg);
|
||||
emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
|
||||
break;
|
||||
}
|
||||
case CmpInst::ICMP_SGT: {
|
||||
EmitInst(Mips::SLT, ResultReg).addReg(RightReg).addReg(LeftReg);
|
||||
emitInst(Mips::SLT, ResultReg).addReg(RightReg).addReg(LeftReg);
|
||||
break;
|
||||
}
|
||||
case CmpInst::ICMP_SLT: {
|
||||
EmitInst(Mips::SLT, ResultReg).addReg(LeftReg).addReg(RightReg);
|
||||
emitInst(Mips::SLT, ResultReg).addReg(LeftReg).addReg(RightReg);
|
||||
break;
|
||||
}
|
||||
case CmpInst::ICMP_SGE: {
|
||||
unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
|
||||
EmitInst(Mips::SLT, TempReg).addReg(LeftReg).addReg(RightReg);
|
||||
EmitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
|
||||
emitInst(Mips::SLT, TempReg).addReg(LeftReg).addReg(RightReg);
|
||||
emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
|
||||
break;
|
||||
}
|
||||
case CmpInst::ICMP_SLE: {
|
||||
unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
|
||||
EmitInst(Mips::SLT, TempReg).addReg(RightReg).addReg(LeftReg);
|
||||
EmitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
|
||||
emitInst(Mips::SLT, TempReg).addReg(RightReg).addReg(LeftReg);
|
||||
emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
|
||||
break;
|
||||
}
|
||||
case CmpInst::FCMP_OEQ:
|
||||
@ -708,11 +734,11 @@ bool MipsFastISel::EmitCmp(unsigned ResultReg, const CmpInst *CI) {
|
||||
}
|
||||
unsigned RegWithZero = createResultReg(&Mips::GPR32RegClass);
|
||||
unsigned RegWithOne = createResultReg(&Mips::GPR32RegClass);
|
||||
EmitInst(Mips::ADDiu, RegWithZero).addReg(Mips::ZERO).addImm(0);
|
||||
EmitInst(Mips::ADDiu, RegWithOne).addReg(Mips::ZERO).addImm(1);
|
||||
EmitInst(Opc).addReg(LeftReg).addReg(RightReg).addReg(
|
||||
emitInst(Mips::ADDiu, RegWithZero).addReg(Mips::ZERO).addImm(0);
|
||||
emitInst(Mips::ADDiu, RegWithOne).addReg(Mips::ZERO).addImm(1);
|
||||
emitInst(Opc).addReg(LeftReg).addReg(RightReg).addReg(
|
||||
Mips::FCC0, RegState::ImplicitDefine);
|
||||
MachineInstrBuilder MI = EmitInst(CondMovOpc, ResultReg)
|
||||
MachineInstrBuilder MI = emitInst(CondMovOpc, ResultReg)
|
||||
.addReg(RegWithOne)
|
||||
.addReg(Mips::FCC0)
|
||||
.addReg(RegWithZero, RegState::Implicit);
|
||||
@ -723,10 +749,10 @@ bool MipsFastISel::EmitCmp(unsigned ResultReg, const CmpInst *CI) {
|
||||
return true;
|
||||
}
|
||||
|
||||
bool MipsFastISel::SelectCmp(const Instruction *I) {
|
||||
bool MipsFastISel::selectCmp(const Instruction *I) {
|
||||
const CmpInst *CI = cast<CmpInst>(I);
|
||||
unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
|
||||
if (!EmitCmp(ResultReg, CI))
|
||||
if (!emitCmp(ResultReg, CI))
|
||||
return false;
|
||||
updateValueMap(I, ResultReg);
|
||||
return true;
|
||||
@ -739,56 +765,56 @@ bool MipsFastISel::fastSelectInstruction(const Instruction *I) {
|
||||
default:
|
||||
break;
|
||||
case Instruction::Load:
|
||||
return SelectLoad(I);
|
||||
return selectLoad(I);
|
||||
case Instruction::Store:
|
||||
return SelectStore(I);
|
||||
return selectStore(I);
|
||||
case Instruction::Br:
|
||||
return SelectBranch(I);
|
||||
return selectBranch(I);
|
||||
case Instruction::Ret:
|
||||
return SelectRet(I);
|
||||
return selectRet(I);
|
||||
case Instruction::Trunc:
|
||||
return SelectTrunc(I);
|
||||
return selectTrunc(I);
|
||||
case Instruction::ZExt:
|
||||
case Instruction::SExt:
|
||||
return SelectIntExt(I);
|
||||
return selectIntExt(I);
|
||||
case Instruction::FPTrunc:
|
||||
return SelectFPTrunc(I);
|
||||
return selectFPTrunc(I);
|
||||
case Instruction::FPExt:
|
||||
return SelectFPExt(I);
|
||||
return selectFPExt(I);
|
||||
case Instruction::FPToSI:
|
||||
return SelectFPToI(I, /*isSigned*/ true);
|
||||
return selectFPToInt(I, /*isSigned*/ true);
|
||||
case Instruction::FPToUI:
|
||||
return SelectFPToI(I, /*isSigned*/ false);
|
||||
return selectFPToInt(I, /*isSigned*/ false);
|
||||
case Instruction::ICmp:
|
||||
case Instruction::FCmp:
|
||||
return SelectCmp(I);
|
||||
return selectCmp(I);
|
||||
}
|
||||
return false;
|
||||
}
|
||||
|
||||
unsigned MipsFastISel::MaterializeFP(const ConstantFP *CFP, MVT VT) {
|
||||
unsigned MipsFastISel::materializeFP(const ConstantFP *CFP, MVT VT) {
|
||||
if (UnsupportedFPMode)
|
||||
return 0;
|
||||
int64_t Imm = CFP->getValueAPF().bitcastToAPInt().getZExtValue();
|
||||
if (VT == MVT::f32) {
|
||||
const TargetRegisterClass *RC = &Mips::FGR32RegClass;
|
||||
unsigned DestReg = createResultReg(RC);
|
||||
unsigned TempReg = Materialize32BitInt(Imm, &Mips::GPR32RegClass);
|
||||
EmitInst(Mips::MTC1, DestReg).addReg(TempReg);
|
||||
unsigned TempReg = materialize32BitInt(Imm, &Mips::GPR32RegClass);
|
||||
emitInst(Mips::MTC1, DestReg).addReg(TempReg);
|
||||
return DestReg;
|
||||
} else if (VT == MVT::f64) {
|
||||
const TargetRegisterClass *RC = &Mips::AFGR64RegClass;
|
||||
unsigned DestReg = createResultReg(RC);
|
||||
unsigned TempReg1 = Materialize32BitInt(Imm >> 32, &Mips::GPR32RegClass);
|
||||
unsigned TempReg1 = materialize32BitInt(Imm >> 32, &Mips::GPR32RegClass);
|
||||
unsigned TempReg2 =
|
||||
Materialize32BitInt(Imm & 0xFFFFFFFF, &Mips::GPR32RegClass);
|
||||
EmitInst(Mips::BuildPairF64, DestReg).addReg(TempReg2).addReg(TempReg1);
|
||||
materialize32BitInt(Imm & 0xFFFFFFFF, &Mips::GPR32RegClass);
|
||||
emitInst(Mips::BuildPairF64, DestReg).addReg(TempReg2).addReg(TempReg1);
|
||||
return DestReg;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
unsigned MipsFastISel::MaterializeGV(const GlobalValue *GV, MVT VT) {
|
||||
unsigned MipsFastISel::materializeGV(const GlobalValue *GV, MVT VT) {
|
||||
// For now 32-bit only.
|
||||
if (VT != MVT::i32)
|
||||
return 0;
|
||||
@ -799,13 +825,13 @@ unsigned MipsFastISel::MaterializeGV(const GlobalValue *GV, MVT VT) {
|
||||
// TLS not supported at this time.
|
||||
if (IsThreadLocal)
|
||||
return 0;
|
||||
EmitInst(Mips::LW, DestReg)
|
||||
emitInst(Mips::LW, DestReg)
|
||||
.addReg(MFI->getGlobalBaseReg())
|
||||
.addGlobalAddress(GV, 0, MipsII::MO_GOT);
|
||||
if ((GV->hasInternalLinkage() ||
|
||||
(GV->hasLocalLinkage() && !isa<Function>(GV)))) {
|
||||
unsigned TempReg = createResultReg(RC);
|
||||
EmitInst(Mips::ADDiu, TempReg)
|
||||
emitInst(Mips::ADDiu, TempReg)
|
||||
.addReg(DestReg)
|
||||
.addGlobalAddress(GV, 0, MipsII::MO_ABS_LO);
|
||||
DestReg = TempReg;
|
||||
@ -813,7 +839,7 @@ unsigned MipsFastISel::MaterializeGV(const GlobalValue *GV, MVT VT) {
|
||||
return DestReg;
|
||||
}
|
||||
|
||||
unsigned MipsFastISel::MaterializeInt(const Constant *C, MVT VT) {
|
||||
unsigned MipsFastISel::materializeInt(const Constant *C, MVT VT) {
|
||||
if (VT != MVT::i32 && VT != MVT::i16 && VT != MVT::i8 && VT != MVT::i1)
|
||||
return 0;
|
||||
const TargetRegisterClass *RC = &Mips::GPR32RegClass;
|
||||
@ -823,19 +849,19 @@ unsigned MipsFastISel::MaterializeInt(const Constant *C, MVT VT) {
|
||||
Imm = CI->getSExtValue();
|
||||
else
|
||||
Imm = CI->getZExtValue();
|
||||
return Materialize32BitInt(Imm, RC);
|
||||
return materialize32BitInt(Imm, RC);
|
||||
}
|
||||
|
||||
unsigned MipsFastISel::Materialize32BitInt(int64_t Imm,
|
||||
unsigned MipsFastISel::materialize32BitInt(int64_t Imm,
|
||||
const TargetRegisterClass *RC) {
|
||||
unsigned ResultReg = createResultReg(RC);
|
||||
|
||||
if (isInt<16>(Imm)) {
|
||||
unsigned Opc = Mips::ADDiu;
|
||||
EmitInst(Opc, ResultReg).addReg(Mips::ZERO).addImm(Imm);
|
||||
emitInst(Opc, ResultReg).addReg(Mips::ZERO).addImm(Imm);
|
||||
return ResultReg;
|
||||
} else if (isUInt<16>(Imm)) {
|
||||
EmitInst(Mips::ORi, ResultReg).addReg(Mips::ZERO).addImm(Imm);
|
||||
emitInst(Mips::ORi, ResultReg).addReg(Mips::ZERO).addImm(Imm);
|
||||
return ResultReg;
|
||||
}
|
||||
unsigned Lo = Imm & 0xFFFF;
|
||||
@ -843,14 +869,13 @@ unsigned MipsFastISel::Materialize32BitInt(int64_t Imm,
|
||||
if (Lo) {
|
||||
// Both Lo and Hi have nonzero bits.
|
||||
unsigned TmpReg = createResultReg(RC);
|
||||
EmitInst(Mips::LUi, TmpReg).addImm(Hi);
|
||||
EmitInst(Mips::ORi, ResultReg).addReg(TmpReg).addImm(Lo);
|
||||
emitInst(Mips::LUi, TmpReg).addImm(Hi);
|
||||
emitInst(Mips::ORi, ResultReg).addReg(TmpReg).addImm(Lo);
|
||||
} else {
|
||||
EmitInst(Mips::LUi, ResultReg).addImm(Hi);
|
||||
emitInst(Mips::LUi, ResultReg).addImm(Hi);
|
||||
}
|
||||
return ResultReg;
|
||||
}
|
||||
}
|
||||
|
||||
namespace llvm {
|
||||
FastISel *Mips::createFastISel(FunctionLoweringInfo &funcInfo,
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user