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Add MachineOperand IsInternalRead flag.

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This flag is used when bundling machine instructions.  It indicates
whether the operand reads a value defined inside or outside its bundle.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145997 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen 2011-12-07 00:22:07 +00:00
parent 26323442d5
commit 2068215e85
2 changed files with 44 additions and 6 deletions
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27
include/llvm/CodeGen/MachineOperand.h
View File

@ -102,6 +102,17 @@ private:
///
bool IsUndef : 1;
/// IsInternalRead - True if this operand reads a value that was defined
/// inside the same instruction or bundle. This flag can be set on both use
/// and def operands. On a sub-register def operand, it refers to the part
/// of the register that isn't written. On a full-register def operand, it
/// is a noop.
///
/// When this flag is set, the instruction bundle must contain at least one
/// other def of the register. If multiple instructions in the bundle define
/// the register, the meaning is target-defined.
bool IsInternalRead : 1;
/// IsEarlyClobber - True if this MO_Register 'def' operand is written to
/// by the MachineInstr before all input registers are read. This is used to
/// model the GCC inline asm '&' constraint modifier.
@ -258,6 +269,11 @@ public:
return IsUndef;
}
bool isInternalRead() const {
assert(isReg() && "Wrong MachineOperand accessor");
return IsInternalRead;
}
bool isEarlyClobber() const {
assert(isReg() && "Wrong MachineOperand accessor");
return IsEarlyClobber;
@ -272,9 +288,12 @@ public:
/// register. A use operand with the <undef> flag set doesn't read its
/// register. A sub-register def implicitly reads the other parts of the
/// register being redefined unless the <undef> flag is set.
///
/// This refers to reading the register value from before the current
/// instruction or bundle. Internal bundle reads are not included.
bool readsReg() const {
assert(isReg() && "Wrong MachineOperand accessor");
return !isUndef() && (isUse() || getSubReg());
return !isUndef() && !isInternalRead() && (isUse() || getSubReg());
}
/// getNextOperandForReg - Return the next MachineOperand in the function that
@ -343,6 +362,11 @@ public:
IsUndef = Val;
}
void setIsInternalRead(bool Val = true) {
assert(isReg() && "Wrong MachineOperand accessor");
IsInternalRead = Val;
}
void setIsEarlyClobber(bool Val = true) {
assert(isReg() && IsDef && "Wrong MachineOperand accessor");
IsEarlyClobber = Val;
@ -498,6 +522,7 @@ public:
Op.IsKill = isKill;
Op.IsDead = isDead;
Op.IsUndef = isUndef;
Op.IsInternalRead = false;
Op.IsEarlyClobber = isEarlyClobber;
Op.IsDebug = isDebug;
Op.SmallContents.RegNo = Reg;

23
lib/CodeGen/MachineInstr.cpp
View File

@ -178,6 +178,7 @@ void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp,
IsKill = isKill;
IsDead = isDead;
IsUndef = isUndef;
IsInternalRead = false;
IsEarlyClobber = false;
IsDebug = isDebug;
SubReg = 0;
@ -256,14 +257,26 @@ void MachineOperand::print(raw_ostream &OS, const TargetMachine *TM) const {
NeedComma = true;
}
if (isKill() || isDead() || isUndef()) {
if (isKill() || isDead() || isUndef() || isInternalRead()) {
if (NeedComma) OS << ',';
if (isKill()) OS << "kill";
if (isDead()) OS << "dead";
NeedComma = false;
if (isKill()) {
OS << "kill";
NeedComma = true;
}
if (isDead()) {
OS << "dead";
NeedComma = true;
}
if (isUndef()) {
if (isKill() || isDead())
OS << ',';
if (NeedComma) OS << ',';
OS << "undef";
NeedComma = true;
}
if (isInternalRead()) {
if (NeedComma) OS << ',';
OS << "internal";
NeedComma = true;
}
}
OS << '>';