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Add a flag for indirect branch instructions.

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Target maintainers: please check that the instructions for your target are correctly marked.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44012 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Owen Anderson 2007-11-12 07:39:39 +00:00
parent f2fbca68f8
commit 20ab29068d
10 changed files with 16 additions and 7 deletions
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5
include/llvm/Target/TargetInstrInfo.h
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@ -48,6 +48,7 @@ const unsigned M_BARRIER_FLAG = 1 << 3;
const unsigned M_DELAY_SLOT_FLAG = 1 << 4;
const unsigned M_LOAD_FLAG = 1 << 5;
const unsigned M_STORE_FLAG = 1 << 6;
const unsigned M_INDIRECT_FLAG = 1 << 7;
// M_CONVERTIBLE_TO_3_ADDR - This is a 2-address instruction which can be
// changed into a 3-address instruction if the first two operands cannot be
@ -237,6 +238,10 @@ public:
return get(Opcode).Flags & M_BRANCH_FLAG;
}
bool isIndirectBranch(MachineOpCode Opcode) const {
return get(Opcode).Flags & M_INDIRECT_FLAG;
}
/// isBarrier - Returns true if the specified instruction stops control flow
/// from executing the instruction immediately following it. Examples include
/// unconditional branches and return instructions.

2
lib/Target/ARM/ARMInstrInfo.td
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@ -773,7 +773,7 @@ let isBranch = 1, isTerminator = 1 in {
def B : AXI<0xA, (outs), (ins brtarget:$target), Branch, "b $target",
[(br bb:$target)]>;
let isNotDuplicable = 1 in {
let isNotDuplicable = 1, isIndirectBranch = 1 in {
def BR_JTr : JTI<0x0, (outs), (ins GPR:$target, jtblock_operand:$jt, i32imm:$id),
"mov pc, $target \n$jt",
[(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]>;

3
lib/Target/Alpha/AlphaInstrInfo.td
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@ -374,8 +374,7 @@ let isReturn = 1, isTerminator = 1, Ra = 31, Rb = 26, disp = 1, Uses = [R26] in
def RETDAGp : MbrpForm< 0x1A, 0x02, (ops), "ret $$31,($$26),1", [(retflag)], s_jsr>; //Return from subroutine
}
let isBranch = 1, isTerminator = 1, isBarrier = 1,
Ra = 31, disp = 0 in
let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1, Ra = 31, disp = 0 in
def JMP : MbrpForm< 0x1A, 0x00, (ops GPRC:$RS), "jmp $$31,($RS),0",
[(brind GPRC:$RS)], s_jsr>; //Jump

3
lib/Target/PowerPC/PPCInstrInfo.td
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@ -369,7 +369,8 @@ let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in {
def BLR : XLForm_2_br<19, 16, 0, (outs), (ins pred:$p),
"b${p:cc}lr ${p:reg}", BrB,
[(retflag)]>;
def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>;
let isBranch = 1, isIndirectBranch = 1 in
def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>;
}

1
lib/Target/Target.td
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@ -187,6 +187,7 @@ class Instruction {
// instruction.
bit isReturn = 0; // Is this instruction a return instruction?
bit isBranch = 0; // Is this instruction a branch instruction?
bit isIndirectBranch = 0; // Is this instruction an indirect branch?
bit isBarrier = 0; // Can control flow fall through this instruction?
bit isCall = 0; // Is this instruction a call instruction?
bit isLoad = 0; // Is this instruction a load instruction?

4
lib/Target/X86/X86InstrInfo.td
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@ -294,11 +294,11 @@ let isBranch = 1, isTerminator = 1 in
class IBr<bits<8> opcode, dag ins, string asm, list<dag> pattern> :
I<opcode, RawFrm, (outs), ins, asm, pattern>;
// Indirect branches
let isBranch = 1, isBarrier = 1 in
def JMP : IBr<0xE9, (ins brtarget:$dst), "jmp\t$dst", [(br bb:$dst)]>;
let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
// Indirect branches
let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
def JMP32r : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst",
[(brind GR32:$dst)]>;
def JMP32m : I<0xFF, MRM4m, (outs), (ins i32mem:$dst), "jmp{l}\t{*}$dst",

2
lib/Target/X86/X86InstrX86-64.td
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@ -120,7 +120,7 @@ let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
[]>;
// Branches
let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
def JMP64r : I<0xFF, MRM4r, (outs), (ins GR64:$dst), "jmp{q}\t{*}$dst",
[(brind GR64:$dst)]>;
def JMP64m : I<0xFF, MRM4m, (outs), (ins i64mem:$dst), "jmp{q}\t{*}$dst",

1
utils/TableGen/CodeGenInstruction.h
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@ -87,6 +87,7 @@ namespace llvm {
// Various boolean values we track for the instruction.
bool isReturn;
bool isBranch;
bool isIndirectBranch;
bool isBarrier;
bool isCall;
bool isLoad;

1
utils/TableGen/CodeGenTarget.cpp
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@ -379,6 +379,7 @@ CodeGenInstruction::CodeGenInstruction(Record *R, const std::string &AsmStr)
isReturn = R->getValueAsBit("isReturn");
isBranch = R->getValueAsBit("isBranch");
isIndirectBranch = R->getValueAsBit("isIndirectBranch");
isBarrier = R->getValueAsBit("isBarrier");
isCall = R->getValueAsBit("isCall");
isLoad = R->getValueAsBit("isLoad");

1
utils/TableGen/InstrInfoEmitter.cpp
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@ -237,6 +237,7 @@ void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num,
// Emit all of the target indepedent flags...
if (Inst.isReturn) OS << "|M_RET_FLAG";
if (Inst.isBranch) OS << "|M_BRANCH_FLAG";
if (Inst.isIndirectBranch) OS << "|M_INDIRECT_FLAG";
if (Inst.isBarrier) OS << "|M_BARRIER_FLAG";
if (Inst.hasDelaySlot) OS << "|M_DELAY_SLOT_FLAG";
if (Inst.isCall) OS << "|M_CALL_FLAG";